EDA Tools — Electronic Design Automation

Electronic design automation (EDA) software is the design infrastructure that makes modern chip development possible. Without EDA, it would be impossible to design, verify, simulate, and sign-off a chip with billions of transistors. EDA tools translate a chip architect's intent -- expressed as hardware description language (HDL) code -- into physical layout data (GDSII/OASIS files) that photomask shops use to produce the reticles that pattern silicon at fabs. Three companies control approximately 75% of the global EDA market: Synopsys, Cadence, and Siemens EDA. This concentration makes EDA software a structural chokepoint in the semiconductor supply chain -- one that the US demonstrated it was willing to weaponize when it directed all three to halt China sales in May 2025.

EDA Vendor Landscape

Company	HQ	Global Market Share	Core Strengths	Key Notes
Synopsys	US (Sunnyvale, CA)	~31%	Logic synthesis (Design Compiler, DC Ultra); formal verification (VCS, Verdi); sign-off (PrimeTime); semiconductor IP (DesignWare)	Largest EDA vendor by revenue; acquiring Ansys for ~$35B (multiphysics simulation integration); China revenue was ~$1B (~16% of total) before 2025 export controls; Synopsys also the largest commercial IP vendor via DesignWare portfolio
Cadence Design Systems	US (San Jose, CA)	~30%	Analog/mixed-signal design (Virtuoso); digital implementation (Innovus); verification (Xcelium, Jasper); chip-package co-design	Leader in analog and custom layout; Virtuoso is the standard platform for analog IC design; China revenue was ~$550M (~12% of total); Cadence also provides Tensilica DSP IP
Siemens EDA (Mentor Graphics)	US (Wilsonville, OR) / Germany (Siemens AG parent)	~13%	DRC/LVS sign-off (Calibre -- dominant tool used by >90% of IC designers); PCB design (PADS, Xpedition); embedded software; system verification	Calibre holds >70% of the DRC/LVS sign-off market -- any chip going to tape-out at any leading foundry passes through Calibre; Siemens AG parent makes export control status complex (German company, US-based EDA subsidiary, US-origin technology)
Ansys	US (Canonsburg, PA)	~5% (EDA-adjacent)	Thermal simulation, electromagnetic simulation, multiphysics for chip, package, and system	Being acquired by Synopsys; integration will add multiphysics sign-off to Synopsys' design-to-silicon platform -- relevant for chiplet thermal management and signal integrity at advanced nodes

EDA Design Workflow

Stage	Process	Primary Tools	Output
RTL Design	Hardware description language (Verilog, VHDL, SystemVerilog) defines logic behavior; architecture and microarchitecture decisions made here	Text editors, version control; RTL linting tools (Mentor, Synopsys)	RTL code (behavioral description of chip function)
Verification	Functional simulation, UVM testbench development, formal verification to confirm RTL behaves as specified; most time-consuming phase at advanced SoCs	Cadence Xcelium, Synopsys VCS (simulation); Cadence Jasper, Synopsys VC Formal (formal verification)	Verified RTL with sign-off on functional correctness
Logic Synthesis	RTL compiled to gate-level netlist using foundry standard cell library; timing, area, and power optimization against foundry PDK constraints	Synopsys Design Compiler / DC Ultra (dominant); Cadence Genus	Gate-level netlist mapped to foundry standard cells
Place & Route	Physical placement of standard cells on chip floorplan; routing of interconnects; timing closure to meet frequency target	Synopsys IC Compiler II; Cadence Innovus	GDSII layout data (physical chip design)
Sign-Off Verification	DRC (design rule check): verifies layout against foundry manufacturing rules. LVS (layout vs schematic): confirms layout matches netlist. STA (static timing analysis): confirms timing is met at all process corners	Siemens Calibre (DRC/LVS -- dominant, >90% market); Synopsys PrimeTime (STA); Ansys RedHawk (power integrity)	Tape-out-ready GDSII; foundry DRC-clean
Tape-Out	Final GDSII submitted to foundry; mask data preparation (MDP) converts GDSII to mask-writer format; reticles fabricated; wafer production begins	Mentor/Siemens Calibre for MDP; foundry PDK-validated flows	Mask files to photomask shop; wafer production commences

China Export Controls: The 2025 Episode

On May 23, 2025, the US Bureau of Industry and Security (BIS) directed Synopsys, Cadence, and Siemens EDA to halt EDA software sales to China without a license, citing the risk of diversion to Chinese military end users for advanced AI chip design. The directive expanded previous restrictions that had primarily targeted sub-14nm and gate-all-around (GAA) design tools -- the 2025 action covered all EDA sales to China subject to case-by-case license review.

The market impact was immediate: Synopsys shares fell 9.6%, Cadence fell 10.7%. China represented approximately $1 billion (16%) of Synopsys' annual revenue and $550 million (12%) of Cadence's. Siemens EDA's Calibre DRC/LVS tool was particularly sensitive -- used by over 90% of IC designers and holding more than 70% of the DRC sign-off market globally, including in China. Cutting off Calibre would effectively halt Chinese chip tape-out at any node.

The restrictions were partially reversed in early July 2025 as part of US-China trade negotiations, with all three vendors restoring access. Synopsys had begun shutting down China operations and reversed course. The episode confirmed that EDA is now an active lever in US-China technology competition -- the software tools that enable chip design are as strategically controlled as the equipment that manufactures chips.

China's Domestic EDA: Empyrean & Alternatives

China's domestic EDA industry exists but operates well below the capability frontier of Western tools, particularly for advanced nodes. Three Chinese companies attracted investor attention following the 2025 export control announcement: Empyrean Technology, Primarius Technologies, and Semitronix. Empyrean is the leading domestic player, reporting approximately 1.22 billion CNY ($168 million) in annual revenue -- roughly 10% of Cadence's China revenue alone.

Empyrean's tools cover point solutions in specific EDA workflow segments but do not offer a complete, integrated suite comparable to Synopsys or Cadence. Critically, Empyrean lacks competitive tools for the most advanced design flows (GAA transistor design at 3nm and below) where Western tools' integration with foundry PDKs and accumulated process knowledge is deepest. Adding complexity, the US added Empyrean Technology to the Entity List in December 2024, potentially restricting its access to certain US-origin technology and components used in its own tool development. Huawei and X-Epic have reportedly developed internal EDA capabilities for specific design tasks, but these are not available as merchant products and are not validated for external foundry tape-outs. A significant portion of Chinese chip designers were reportedly using pirated Western EDA software -- a baseline that would be disrupted by strict enforcement.

Supply Chain Outlook

The EDA market's ~75% concentration in three US/German-based companies makes it a uniquely concentrated design infrastructure chokepoint. First-time tape-out success rates have reportedly fallen to a historic low of approximately 14% at advanced nodes -- eight of ten chip designs fail the first attempt -- reflecting the complexity of designing at 3nm and below. This failure rate increases dependence on EDA vendors for verification and sign-off tools that catch errors before tape-out. The Synopsys-Ansys merger will add multiphysics simulation (thermal, electromagnetic) to the design-to-silicon platform, relevant for advanced packaging and chiplet thermal management. The 2025 China export control episode and its rapid reversal suggests EDA controls will remain a recurring tool in US-China technology negotiations rather than a settled policy.

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