SemiconductorX > Fab & Assembly > Manufacturing Flow > Front-End Fabrication > Wafer Oxidation
Wafer Oxidation
Oxidation grows a layer of silicon dioxide (SiO₂) directly on the silicon wafer by reacting the silicon surface with oxygen or water vapor at high temperature. Unlike deposition, where material is added on top of the wafer, thermal oxidation consumes silicon from the wafer surface and converts it to oxide — the oxide grows both into the wafer and above the original surface. The resulting SiO₂ film is the highest-quality insulator that can be produced on silicon: uniform, defect-free, with a near-atomically-perfect interface to the underlying silicon.
Oxidation is a conditional step in the front-end loop, not a loop step itself. It is invoked selectively — for shallow trench isolation (STI) liners, for sacrificial oxides that protect the wafer during ion implantation, for surface passivation between process modules, and historically for gate dielectric before high-k/metal gate displaced thermal SiO₂ at sub-45nm logic. Concentration in oxidation equipment is tight: four vendors — Kokusai Electric, Tokyo Electron, ASM International, and Applied Materials — supply essentially all thermal oxidation furnaces and RTP tools globally. Consumable supply is the bulk-gas oligopoly covered under Process Consumables, with high-purity quartz tubes as a specialty consumable with its own small supplier base.
Where Oxidation Happens in the Flow
Oxidation is applied multiple times during front-end fabrication, at specific points where a high-quality SiO₂ film is needed. Unlike deposition or etch, which run dozens of times across every layer, oxidation runs a handful of times at transistor-formation stages.
| Use | Purpose | Typical Thickness |
|---|---|---|
| Pad oxide | Thin buffer oxide before nitride deposition for STI definition | 5–15 nm |
| STI liner oxide | Oxide liner inside the etched trench before STI fill; reduces defects at the silicon/oxide interface | 5–20 nm |
| Sacrificial oxide | Temporary protective oxide before or after ion implantation; stripped later | 10–30 nm |
| Gate oxide (legacy / specialty) | Gate dielectric in mature-node CMOS, power devices, analog, MEMS | 1.5–10 nm |
| Interfacial oxide (advanced logic) | Ultra-thin SiO₂ under the high-k dielectric in HKMG stacks | ~1 nm |
| Field oxide (legacy) | Thick isolation oxide in LOCOS-era processes; largely displaced by STI | 200–500+ nm |
| Power device oxide | Gate and field oxide in SiC and Si power MOSFETs | 50–200 nm |
Dry vs. Wet Oxidation
Oxidation divides into two chemistries based on the oxidant. Dry oxidation uses pure oxygen (O₂) and produces the highest-quality films at the cost of growth rate. Wet oxidation uses water vapor (steam) or pyrogenic H₂/O₂ and produces thicker films much faster, at the cost of film density and interface quality. Each mode dominates a specific range of thickness and quality requirements.
| Attribute | Dry Oxidation (O₂) | Wet Oxidation (H₂O / Steam) |
|---|---|---|
| Growth rate | Slow | Fast (roughly 5–10× dry) |
| Typical thickness range | 1–20 nm | 20 nm to 500+ nm |
| Film quality | Highest density; lowest defects; best Si/SiO₂ interface | Lower density; hydrogen incorporation; acceptable for isolation |
| Temperature | ~900–1150 °C | ~900–1100 °C |
| Primary applications | Gate oxide, thin interfacial oxide, pad oxide, precise isolation interfaces | Field oxide, sacrificial oxide, power device oxides, thick isolation |
| Thermal budget | High (long time for target thickness) | High but throughput-favorable due to faster growth |
Rapid thermal oxidation (RTO) — a variant performed in a single-wafer RTP chamber at short durations — has largely replaced batch furnace oxidation for the thinnest layers at advanced nodes, where thickness control below 2 nm and minimal thermal budget both matter.
Equipment
Oxidation runs on two tool architectures: vertical batch furnaces, which process 25 to 150 wafers per run at high throughput and are standard for mature-node fabs and thick-oxide applications, and single-wafer rapid thermal processing (RTP) chambers, which provide the precise thickness control and minimal thermal budget required for advanced-node thin oxides. Equipment supply concentrates at four vendors.
| Vendor | HQ | Primary Platforms |
|---|---|---|
| Kokusai Electric | Japan | Vertical batch furnaces for oxidation, diffusion, and LPCVD; dominant in Asian fabs |
| Tokyo Electron (TEL) | Japan | Vertical batch furnaces widely deployed in 200mm and 300mm fabs |
| ASM International | Netherlands | Rapid thermal oxidation systems; ALD-integrated thermal tools for advanced nodes |
| Applied Materials | United States | RTP platforms with oxidation capability; integrated into advanced logic process flows |
Consumables & Utilities
Oxidation consumes high-purity oxygen, hydrogen (for pyrogenic steam generation), and nitrogen for purge and dilution. Bulk gas supply is the four-company industrial gas oligopoly: Air Liquide, Linde, Air Products, and Taiyo Nippon Sanso. Wet oxidation requires either ultra-high-purity water vapor sources or in-situ pyrogenic steam generation from H₂ and O₂, both of which are supplied through the same gas delivery infrastructure. The furnace tubes, liners, and wafer boats that withstand the 1000+ °C operating environment are made of high-purity synthetic quartz supplied by specialty vendors including Heraeus, Shin-Etsu Quartz, Tosoh, and Momentive — a small supplier base for a critical high-temperature consumable. See Process Consumables for the broader consumables view.
Why Thermal SiO₂ Matters Less at Advanced Logic
Thermal oxide dominated gate dielectric from the 1960s through roughly the 45nm generation. Below that node, continued scaling drove the equivalent oxide thickness toward 1 nm, at which point direct tunneling leakage through the thin SiO₂ became uncontrollable. The industry response was high-k metal gate (HKMG) stacks: a thin interfacial SiO₂ (grown thermally) capped with a high-k dielectric (typically hafnium oxide, HfO₂) deposited by ALD. Thermal oxidation persists in this flow for the interfacial layer, but the bulk of the gate dielectric stack is now deposited rather than thermally grown.
Thermal oxidation remains essential for isolation (STI liners), for sacrificial steps, for surface passivation, and for power device applications where thick gate and field oxides are structural. Silicon carbide (SiC) power MOSFETs in particular rely on thermal oxidation for gate oxide, though SiC oxidation has its own chemistry challenges (interface traps, lower growth rates on the SiC face) and is an active area of process development. See Process Nodes & Lines for the transistor architecture progression and SiC & GaN Power Modules for wide-bandgap device context.
Related Coverage
Parent: Front-End Fabrication
Peers in front-end: Wafer Cleaning · Deposition · Photolithography · Etching · Doping · CMP · Metrology
Equipment & consumables: WFE Hub · Process Consumables · Process Gases
Cross-pillar dependencies: Process Nodes & Lines · SiC & GaN Power Modules · Bottleneck Atlas