Silicon Wafer Production Overview

Silicon wafer production is the bridge between polysilicon feedstock and the semiconductor fab. It converts ultra-pure polysilicon chunks into the precisely dimensioned, mirror-flat, defect-free substrates that every chip begins with. The process spans crystal growing, ingot shaping, wire saw slicing, lapping, chemical etching, polishing, and inspection -- each step building on the last, and each defect introduced propagating forward through the entire fabrication sequence. The supply chain is controlled by five companies that collectively hold approximately 85-90% of global 300mm wafer capacity, making silicon wafer production one of the most concentrated segments in the semiconductor materials layer.

Production Process Flow

Step	Method / Equipment	Output	Key Specification	Detail Page
1. Crystal Growing	Czochralski (CZ): polysilicon melted in quartz crucible; seed crystal pulled upward while rotating. Float Zone (FZ): RF induction heating passes along polysilicon rod; no crucible contact	Single-crystal silicon boule (ingot), typically 1-2m long, up to 300mm diameter	CZ: oxygen content ~10¹⁸ atoms/cm³; FZ: oxygen <10¹⁵ atoms/cm³, max 200mm diameter. SiC uses Physical Vapor Transport (PVT) at 2,100-2,400°C	Crystal Growing
2. Ingot Shaping	Cylindrical grinding to target diameter; orientation flat or notch grinding; crop saw removes seed and tail ends	Cylindrical ingot at precise target diameter with crystal orientation markers	Diameter tolerance ±0.5mm; notch (300mm) or flat (≤200mm) defines crystal axis for automated fab handling	Silicon Ingots
3. Wafer Slicing	Multi-wire diamond wire saw; hundreds of parallel wires advance simultaneously through the ingot with abrasive cutting action and water-based coolant	As-sliced wafer discs; rough surface with subsurface saw damage	Target thickness ~775µm (300mm wafer); kerf loss ~100-150µm per cut; bow <60µm as-sliced; TTV <5µm	Wafer Slicing
4. Lapping & Chemical Etching	Lapping: both surfaces ground between rotating cast-iron plates with alumina slurry. Chemical etching: HNA (HF/HNO3/acetic acid) or KOH removes residual damage and surface stress	Stress-relieved wafer with reduced bow and TTV; surface roughened to Ra ~0.3-1µm	Lapping removes ~20-40µm per side; etch removes ~10-20µm per side; bow reduced to <30µm	Wafer Polishing
5. Double-Side Polishing (DSP)	Both wafer surfaces polished simultaneously between upper and lower polishing plates using colloidal silica slurry and polyurethane pads; carrier wafers hold silicon during polishing	Globally flat wafer; GBIR <1µm; TTV <0.5µm; surface Ra ~0.5nm	GBIR (global flatness) <1µm; wafer achieves geometry suitable for lithography chuck contact uniformity	Wafer Polishing
6. Single-Side CMP (Final Polish)	Front surface polished only; alkaline colloidal silica slurry on soft polishing pad; removes DSP micro-roughness to achieve mirror finish	Prime polished wafer ready for fab delivery or epitaxy	Ra <0.1nm RMS; SFQR (site flatness) <130nm for ArF immersion; LPD <20 at 65nm threshold; metal contamination <10¹⁰ atoms/cm²	Wafer Polishing
7. Epitaxy (optional value-add)	CVD reactor (Applied Materials Centura Epi; ASM Epsilon) grows thin single-crystal silicon layer on polished substrate using TCS, DCS, or SiH4 precursor at 1,050-1,200°C	Epi wafer with device-quality epitaxial layer independently doped from substrate	Epi thickness typically 2-8µm for CMOS; resistivity spec per device requirement; thickness uniformity ±1-2%	Specialty Silicon Wafers: Epi, SOI & FZ
8. Inspection & Packaging	Laser surface scanner (KLA, Hitachi) for particles and LPDs; capacitance gauge for thickness/TTV; optical/AFM for surface roughness; laser marking for wafer ID; FOUP/cassette loading	Lot-released, FOUP-loaded fab-ready wafers; full traceability from ingot to lot	All prime specification limits verified; 100% visual inspection; sampled dimensional and surface metrology per lot	Wafer Deliverables

Supplier Landscape & Geographic Concentration

Five producers hold approximately 85-90% of global 300mm silicon wafer capacity. The top two -- Shin-Etsu Chemical and Sumco -- are both Japanese and together control approximately 50% of global 300mm supply. This Japan concentration is a structural supply chain dependency analogous to ASML's position in EUV lithography: a single-country chokepoint for the upstream silicon substrate that every advanced logic, memory, and foundry chip begins with.

Supplier	HQ	Est. 300mm Share	Key Capabilities & Notes
Shin-Etsu Chemical (SEH)	Japan	~27%	World's largest silicon wafer producer; polished prime, epi, SOI; Japan and Singapore plants; CHIPS Act-supported 300mm expansion in Sherman, Texas underway; customer qualification 2-4 years
Sumco	Japan	~24%	Japan primary; polished prime and epi; advanced DRAM and GPU-optimized 300mm wafers; strong in high-purity, low-defect specifications for memory fabs
GlobalWafers	Taiwan	~17%	Polished, epi, SOI, specialty RF and power epi; 300mm and 200mm; developing SiC substrate capability; capacity expansion to support CHIPS Act fab ramp
Siltronic	Germany	~12%	European supply anchor; polished, epi, FZ, SOI; 300mm and 200mm; strong in FZ silicon (low-oxygen, high-resistivity) for power and RF applications; GlobalWafers acquisition attempt blocked by EU regulators
SK Siltron	South Korea	~9%	Samsung subsidiary; primary supplier into Samsung memory and foundry; also produces SiC epiwafers via acquired DuPont SiC unit; 300mm and 200mm

Wafer Size Economics

Larger wafer diameters reduce the cost per die by increasing the number of chips per wafer and improving edge-loss economics. The transition from 200mm to 300mm delivered approximately 2.25x more die area per wafer -- translating, at comparable process costs, to a 30-40% reduction in cost per chip. Every generation transition requires a complete replacement of the wafer handling, slicing, and polishing infrastructure, plus re-qualification of every process step at the new diameter. The 300mm transition took the industry roughly a decade and required near-simultaneous commitment from foundries, IDMs, wafer suppliers, and equipment makers.

The proposed 450mm transition -- which would provide another 2.25x area increase -- has been deferred indefinitely. The equipment ecosystem (slicers, polishers, CMP tools, lithography scanners) would all require redesign at enormous capital cost, and no single company has been willing to make the commitment without the others. At current 300mm wafer economics, the incremental yield benefit of 450mm does not justify the transition investment for any near-term node. 450mm remains an occasional research topic, not an industry program.

Section Pages

Page	Covers
Crystal Growing	CZ vs FZ vs SiC PVT methods; oxygen management; energy consumption; supplier landscape; 300mm vs 200mm market; 450mm status
Silicon Ingots	Ingot shaping, diameter grinding, orientation marks, crop saw operations, ingot-to-wafer yield
Wafer Slicing	Diamond wire vs slurry wire; kerf loss economics; bow and warp control; SiC slicing challenges; Disco, Meyer Burger, Takatori equipment
Wafer Polishing & CMP	Full lapping → chemical etch → DSP → CMP → cleaning sequence; prime wafer surface specifications (GBIR, SFQR, Ra, LPD); SOI and epi additional steps
Specialty Silicon Wafers: Epi, SOI & FZ	CVD epitaxy (TCS/DCS/SiH4 precursors); epi layer types; SOI Smart Cut technology; Soitec FD-SOI near-monopoly; FZ silicon properties and applications
Wafer Deliverables	Diameter formats; wafer types (prime, epi, SOI, test); surface preparation; FOUP/SMIF shipping; supplier table
Incoming Wafer Specifications	Fab-side view: crystal orientation, resistivity, conductivity type, compound wafer orientations, incoming QC dock-to-stock, procurement spec requirements
Compound & Specialty Wafers	SiC, GaAs, InP, GaN, and sapphire wafer supply chains; growth methods; supplier landscape; cross-links to SiC, GaAs/InP, and GaN epiwafer pages

Supply Chain Outlook

Silicon wafer supply is structurally adequate for mature nodes but capacity-constrained for 300mm advanced node production, where qualification timelines of 2-4 years and the high capital cost of new wafer capacity limit new entrant viability. Japan's dominance at positions one and two -- Shin-Etsu and Sumco together at approximately 50% of 300mm capacity -- is not changing in the near term; Shin-Etsu's Texas expansion and GlobalWafers' capacity growth diversify geography but do not change the fundamental oligopoly structure. The 200mm market faces a different constraint: established fabs are fully utilized, new 200mm equipment is scarce, and the automotive and IoT demand surge has not been matched by proportional new supply investment -- a dynamic covered in depth on the Mature Node MCU / $2 Chip Paradox page. Compound wafer supply (SiC, GaAs, InP, GaN) is addressed separately in the Compound & Specialty Wafers section.

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