Datacenter / HPC
Semiconductors

The datacenter and high-performance computing sector is the largest single consumer of semiconductor capital expenditure in the world when measured by total system value, and the sector undergoing the most rapid architectural transformation in its history. Two structural forces are driving simultaneous change. First, the AI infrastructure buildout is layering a new high-density compute tier - GPU and accelerator clusters with 10-120kW per rack power density - on top of the existing general-purpose cloud compute base. Second, the x86 server CPU architecture that has dominated datacenter compute since the 1990s is losing ground to ARM-based designs at the hyperscaler level, driven by power efficiency economics and the vertical integration strategies of AWS (Graviton), Microsoft (Cobalt), Google (Axion), and Ampere Computing. Both forces are reshaping semiconductor supply chains simultaneously and in ways that interact with each other.

The SX editorial boundary between this page and the AI & ML sector page is deliberate. The AI sector page owns the accelerator supply chain - GPU dies, HBM, CoWoS, and custom ASIC programs at hyperscalers. This page owns the general-purpose datacenter semiconductor stack: server CPUs, DDR5 server DRAM, NVMe storage controllers, Ethernet switch ASICs, data processing units (DPUs), power delivery silicon, and the infrastructure semiconductor layer that supports both conventional cloud workloads and AI cluster deployments. The two sectors share physical infrastructure but have distinct semiconductor supply chains and distinct supply chain risk profiles.

Related Coverage: CPUs | Memory & Storage | FPGAs | ASICs | GPU & CPU Boards | AI & ML Sector | Bottleneck Atlas

Semiconductor Device Map — Datacenter / HPC

The x86-to-ARM Server CPU Transition

The most structurally significant long-term shift in datacenter compute silicon is the erosion of x86 dominance by ARM-based server CPUs. This transition is not driven by a single technical breakthrough - it is driven by the compounding of three simultaneous advantages that ARM designs hold over x86 at cloud-native workloads. First, power efficiency: ARM Neoverse cores achieve comparable integer compute performance to x86 cores at significantly lower power draw, which matters enormously at hyperscaler scale where electricity cost dominates total cost of ownership. Second, die cost: ARM server SoCs designed without the legacy x86 instruction set compatibility overhead can be implemented more efficiently at a given node, reducing die area and cost per core. Third, vertical integration: the hyperscalers designing their own ARM CPUs (AWS Graviton, Google Axion, Microsoft Cobalt) capture the margin previously paid to Intel and AMD, control their own performance and power roadmaps, and can differentiate their cloud offerings based on custom silicon that competitors cannot replicate.

AWS Graviton is the most mature and commercially significant hyperscaler ARM CPU program. Graviton4 (TSMC N5, ARM Neoverse V2 core architecture) delivers approximately 30% better performance per watt than the comparable Graviton3 generation and is the default CPU for a growing share of AWS EC2 general-purpose compute. Google's Axion (also ARM Neoverse V2, TSMC N5) is deployed in Google Cloud and Google's internal infrastructure. Microsoft's Cobalt 100 (ARM Neoverse N2) entered Azure deployments in 2024 for general-purpose cloud workloads. Ampere Computing's AmpereOne (up to 192 ARM Neoverse N-class cores, TSMC N5) targets cloud-native workloads at external cloud customers who want ARM efficiency without building their own design program.

The supply chain implication is a structural demand shift at TSMC: ARM server CPU programs are consuming TSMC N5 wafer starts that would previously have gone to Intel-manufactured Xeon (Intel internal fabs) or to AMD EPYC (TSMC N5/N4, which is not new demand). The ARM server CPU share of TSMC N5 is growing every year as Graviton, Axion, and Cobalt programs scale. This adds to - not substitutes for - NVIDIA AI GPU demand at N5, tightening the overall N5 allocation picture further.

Server CPU Landscape

CXL Memory — The Emerging Supply Chain

Compute Express Link (CXL) is a cache-coherent interconnect standard built on top of PCIe 5.0 physical layer that enables direct memory sharing and pooling between CPUs, GPUs, and memory expansion devices. CXL memory expansion modules - essentially DRAM attached to a server over CXL rather than via the CPU's native DRAM channels - allow datacenter operators to disaggregate compute and memory capacity, reducing stranded memory in lightly loaded servers and enabling memory pooling across multiple compute nodes. The practical effect is a new semiconductor supply chain: CXL memory module controllers, CXL switches, and CXL-attached DRAM that is distinct from both conventional server DRAM and HBM.

Samsung and SK Hynix have both announced CXL memory module products targeting datacenter deployments. Samsung's CMM-D (CXL Memory Module - DRAM) products are in early commercial deployment at cloud customers. The supply chain for CXL is still forming - CXL controller ASICs from Marvell, Montage Technology, and others are in qualification; CXL switch silicon from Microchip and Synopsys is at early commercial stage; and the PCIe 5.0 retimer ICs required for CXL signal integrity are a growing sub-category served by Parade Technologies, Montage, and Astera Labs. CXL represents a new demand vector for DRAM that is distinct from HBM (which serves accelerators) and conventional DRAM (which serves server CPU channels) - and its supply chain maturity lags approximately 2-3 years behind the standards work that preceded it.

HPC and National Supercomputer Programs

High-performance computing supercomputers represent the extreme end of datacenter semiconductor density and are the proving ground for technologies that later migrate to commercial cloud infrastructure. The US Department of Energy's Frontier supercomputer at Oak Ridge National Laboratory (peak 1.2 exaFLOPS, AMD EPYC CPUs and AMD Instinct MI250X GPUs) was the first exascale system; Aurora at Argonne National Laboratory (Intel Xeon Sapphire Rapids CPUs and Intel Ponte Vecchio GPU accelerators) is the second. Europe's Jupiter supercomputer at Forschungszentrum Jülich uses NVIDIA Grace Hopper Superchip. Japan's Fugaku (ARM A64FX processor developed by Fujitsu) demonstrated that custom ARM HPC processors can outperform x86 at scale.

The semiconductor supply chain significance of national HPC programs is threefold. First, they are the primary validation environment for new processor generations - Intel Ponte Vecchio, AMD Instinct MI250X, and NVIDIA Grace Hopper Superchip all entered volume production validated through HPC program deployments before broad commercial availability. Second, they create concentrated single-system demand for very large quantities of specific chips - a single exascale system may consume tens of thousands of accelerator cards - which can meaningfully affect supply availability for commercial customers during the procurement window. Third, sovereign HPC programs in Europe, Japan, China, and India are creating demand for domestically designed or domestically manufactured silicon that is reshaping foundry and design ecosystem investment patterns.

Datacenter Power Architecture — The 48V Transition

The AI-driven increase in per-rack power density is forcing a structural change in datacenter power delivery architecture. Conventional datacenters operate on 12V server bus power, which was adequate when rack power densities were 5-10kW. AI GPU racks - particularly NVIDIA GB200 NVL72 configurations drawing 120kW per rack - cannot be efficiently powered at 12V over the cable lengths and bus widths practical in a server rack. The industry is transitioning to 48V rack power architecture, where power is distributed at 48V to the rack and converted to lower voltages at the server or board level by GaN-based point-of-load converters.

The Open Compute Project (OCP) 48V rack power standard is the primary industry alignment mechanism for this transition. Meta, Google, Microsoft, and AWS are all OCP members and have adopted or committed to 48V rack power in new datacenter builds. The semiconductor supply chain consequence is direct: GaN power ICs (Navitas NV6128, TI LMG3522, Infineon CoolGaN) that perform the 48V-to-point-of-load conversion are the enabling device for AI-density rack power. Digital PWM controller ICs from Renesas, Monolithic Power Systems, and TI control the power conversion sequence. Vicor's 48V factorized power architecture modules are an alternative approach using proprietary power ICs. The combined GaN PSU and VRM IC demand from datacenter power architecture transition is a growing and underappreciated supply chain requirement that intersects with GaN demand from EV onboard chargers and industrial power conversion.

Supply Chain Bottlenecks and Risk Factors (2026-2030)

Key Datacenter / HPC Semiconductor Suppliers

Cross-Sector Convergence

Datacenter semiconductors intersect three significant cross-sector supply chain dynamics. First, the TSMC N5 allocation competition: ARM server CPUs at hyperscalers (Graviton4, Axion, Cobalt, AmpereOne) compete for TSMC N5 wafer starts against AI GPU programs, mobile SoCs, automotive ADAS compute, and AMD's own EPYC client programs. As ARM server CPU deployments scale from 30-40% of new hyperscaler CPU installations today toward potential majority share by 2028-2030, the TSMC N5 demand from this category alone will be structurally significant even before accounting for AI and mobile.

Second, the GaN power delivery convergence: the datacenter transition to 48V rack power architecture drives GaN PSU IC demand from the same supply base serving EV onboard chargers, industrial power conversion, and robot joint motor drives. GaN is not a commodity - it is a specialty semiconductor manufactured at TSMC and TI internal fabs with limited capacity expansion pace. The simultaneous surge in datacenter GaN demand (48V AI rack PSU) and EV GaN demand (800V OBC) and robotics GaN demand (joint drive ICs) is not coordinated and is not reflected in any single supplier's disclosed capacity expansion plan. The combined demand trajectory makes GaN capacity expansion decisions in 2025-2026 critically important across multiple sectors simultaneously.

Third, the optical interconnect compound semiconductor supply: coherent optical transceivers for datacenter interconnect use indium phosphide (InP) laser diodes and electro-absorption modulators manufactured at III-V compound semiconductor fabs - a separate and smaller supply chain than silicon. Coherent Corp, Lumentum, and II-VI/Coherent are the primary InP component suppliers. As datacenter bandwidth scaling accelerates with AI cluster buildout (800G to 1.6T to co-packaged optics), InP laser component supply becomes a binding constraint upstream of the transceiver DSP ASIC supply chain. This is the optical equivalent of the SiC substrate constraint in power semiconductors - a physical material supply limit that cannot be resolved by adding CMOS foundry capacity.

Related Coverage: CPUs | Memory & Storage | HBM | FPGAs | ASICs | CoWoS Packaging | Bottleneck Atlas | AI & ML | 5G/6G & Wireless | SiC & GaN Power Modules

Cross-Network: ElectronsX Demand Side

Datacenter semiconductor demand intersects EX coverage at the data center power infrastructure layer - the grid connection, UPS systems, cooling infrastructure, and on-site generation that enable hyperscale compute at the power densities AI clusters require.

EX: Supply Chain Convergence Map | EX: BESS Supply Chain | EX: Electrification Bottleneck Atlas

Key Questions — Datacenter / HPC Semiconductors

Is ARM actually displacing x86 in the datacenter? At hyperscalers, yes - and the displacement is structural rather than cyclical. AWS, Google, and Microsoft have each committed capital and engineering resources to multi-year ARM CPU programs that cannot be easily reversed. The economics are compelling: ARM server CPUs deliver 30-40% better performance per watt at cloud-native workloads, and hyperscalers operate at a scale where electricity cost differences translate directly to hundreds of millions of dollars in annual savings. For enterprise datacenters with large x86 software portfolios and ISV certification requirements, x86 will remain dominant through 2030 - ARM's datacenter disruption is concentrated at the hyperscaler layer where workloads are containerized and software compatibility is less constraining.

What is the significance of Intel 18A for the server CPU market? Intel 18A is Intel's attempt to recover process leadership using gate-all-around (GAA) transistors and PowerVia backside power delivery on the same chip - two major architectural innovations simultaneously. If Intel 18A matures to commercial yield by 2026, Xeon Clearwater Forest could close the performance-per-watt gap with AMD EPYC Turin and TSMC-manufactured ARM server CPUs. If Intel 18A yield does not mature, Intel will need to outsource Xeon production to TSMC, which adds TSMC N3/N2 demand and further tightens leading-edge foundry allocation - while also being a strategic defeat for Intel's foundry ambitions. The 18A outcome is the single most consequential binary event in server CPU supply chains through 2027.

How does the datacenter sector relate to the AI sector on this site? The AI sector page covers the accelerator supply chain: GPU dies (TSMC N3/N5), HBM memory stacks (SK Hynix, Samsung, Micron), CoWoS advanced packaging (TSMC), and custom hyperscaler ASICs. This page covers the surrounding infrastructure semiconductor stack: the host server CPUs that manage GPU nodes, the DDR5 DRAM that buffers data for GPU processing, the Ethernet switch ASICs that interconnect GPU servers, the DPUs that offload networking from host CPUs, and the GaN power delivery ICs that feed the whole system. These are distinct supply chains with distinct constraints and distinct lead times, but they must scale together - a datacenter operator cannot deploy GPU capacity without the surrounding infrastructure silicon.

What is co-packaged optics and why does it matter for supply chains? Co-packaged optics (CPO) integrates optical transceiver functionality directly into the switch ASIC package rather than using pluggable optical modules connected via a faceplate port. The advantage is bandwidth density and power efficiency - CPO eliminates the SerDes electrical interface between switch ASIC and pluggable module, which becomes the power and bandwidth bottleneck at 1.6T and beyond. The supply chain implication is significant: CPO requires the co-design and co-manufacturing of silicon photonic integrated circuits (PICs) with switch ASICs in the same package, creating a new class of semiconductor product that bridges CMOS foundry supply chains and III-V compound semiconductor supply chains. Neither Broadcom, Marvell, nor the optical transceiver suppliers have fully mature CPO supply chains - which is why the transition from pluggable to CPO will take until 2028-2030 even as the bandwidth requirements are pressing against pluggable limits today.

Related Coverage

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