Advanced Packaging (Overview)

Advanced packaging is the multi-die integration half of stage 3 in the manufacturing flow. Where traditional back-end assembly wraps a single die in a protective package, advanced packaging combines multiple dies — logic, memory, I/O, accelerators, sensors — into a single integrated module through high-density interconnect. The technology catalog includes fan-out wafer-level packaging (FOWLP), 2.5D architectures with side-by-side dies on a silicon interposer or silicon bridge, and 3D architectures with dies stacked vertically through through-silicon vias (TSVs) or copper-to-copper hybrid bonds.

Advanced packaging has become the semiconductor industry's most strategic supply chain choke point outside of EUV lithography. As transistor scaling has slowed, packaging has taken over as the primary lever on system performance. TSMC's CoWoS capacity is the single binding global constraint on the AI accelerator market — every NVIDIA H-series, B-series, and Rubin GPU; every AMD MI300 and MI400 series accelerator; and most hyperscaler custom AI silicon depend on CoWoS allocation. Ajinomoto Build-up Film (ABF) is near-sole-sourced for the laminate used in advanced FCBGA substrates. Hybrid bonding equipment, required for sub-10 µm pitch 3D integration, concentrates at BESI (in partnership with Applied Materials) and Tokyo Electron. These concentration points, together, mean that advanced packaging capacity is now a national security consideration in US and allied industrial policy, alongside leading-edge fab capacity.

The Advanced Packaging Landscape

Advanced packaging architectures divide into three families by physical integration style: fan-out (RDL routing on a reconstituted wafer or panel), 2.5D (side-by-side dies on an interposer or bridge), and 3D (vertically stacked dies). Each foundry operates branded implementations of these architectures, and each implementation has its own supply chain, customer base, and capacity profile.

2.5D Architectures

2.5D integration places multiple dies side-by-side on a shared interconnect layer. The shared layer can be a full silicon interposer (CoWoS, I-Cube), a smaller silicon bridge embedded in the organic substrate (EMIB), or an RDL interposer. 2.5D provides the high bandwidth and low latency required for AI accelerators with multiple HBM stacks connected to a logic die, without the thermal and manufacturing complexity of full 3D stacking.

CoWoS (TSMC) is the dominant 2.5D architecture by revenue and strategic importance. CoWoS bonds multiple dies — typically a logic die plus two, four, eight, or more HBM stacks — onto a silicon interposer. The interposer is fabricated at TSMC's back-end-of-line facilities; the assembled CoWoS module is then mounted on an organic substrate for board-level connection. CoWoS has several variants: CoWoS-S with a silicon interposer (the classic architecture), CoWoS-R with an RDL-based interposer (lower cost, lower bandwidth), and CoWoS-L with a local silicon interconnect (bridge-based, similar concept to EMIB). CoWoS capacity has been the binding constraint on AI accelerator production since 2023; TSMC has roughly doubled CoWoS capacity annually but demand continues to outrun supply.

EMIB (Intel) embeds a small silicon bridge into an organic substrate to provide high-density die-to-die interconnect only where needed, avoiding the cost of a full silicon interposer. EMIB is the technology behind Intel Sapphire Rapids server CPUs with HBM, and multi-tile chiplet products. EMIB's cost advantage over full-interposer 2.5D is significant at moderate bandwidth requirements.

I-Cube (Samsung Foundry) is Samsung's 2.5D silicon interposer architecture, structurally similar to CoWoS. I-Cube serves Samsung Foundry customers requiring HBM integration, though its revenue scale and customer base remain smaller than CoWoS.

3D Architectures

3D integration stacks dies vertically, interconnected either through through-silicon vias (TSVs) with solder micro-bumps or, in the newest generation, through direct copper-to-copper hybrid bonding that eliminates the bumps entirely. 3D provides the shortest possible interconnect paths (micrometers rather than millimeters), lowest latency, and highest density — but at the cost of much tighter thermal design and yield sensitivity (a bad die in a stack scraps the stack).

Foveros (Intel) is Intel's 3D die-stacking architecture, used in Meteor Lake and subsequent client CPUs where compute, graphics, I/O, and SoC tiles are stacked on a base die. Original Foveros uses TSV-plus-micro-bump interconnect; Foveros Direct replaces the micro-bumps with direct copper-copper hybrid bonding for much finer pitch (sub-10 µm) and higher interconnect density.

SoIC (TSMC) is TSMC's 3D architecture using copper-copper hybrid bonding. SoIC enables die-on-die stacking without an intermediate interposer layer, targeting performance applications where interconnect density and thermal proximity are paramount. SoIC is positioned as the 3D complement to CoWoS (which handles 2.5D).

HBM stacking is itself a 3D packaging technology, and it has become the volume driver for 3D integration overall. Each HBM die stack contains 8, 12, or 16 DRAM dies stacked with TSVs plus a base logic die; HBM4 (ramping through 2026) will be the first generation using hybrid bonding at the die-to-die interface, substantially reducing stack height and improving thermal performance. See HBM for the memory-side view.

Fan-Out Architectures

Fan-out packaging redistributes the die's I/O pads over a larger area than the die itself by embedding the die in a reconstituted wafer or panel and building RDL (redistribution layer) routing on top. This enables much higher pin count than the die alone could support, eliminates the need for an organic substrate for many applications, and produces very thin packages ideal for mobile.

InFO (Integrated Fan-Out, TSMC) is TSMC's proprietary fan-out architecture, used in Apple A-series and M-series SoCs and in selected other mobile and wearable applications. InFO-PoP (Package-on-Package) integrates memory on top of the logic die in a compact stack; InFO-oS stacks multiple dies with fan-out RDL; InFO_SoW (System-on-Wafer) produces wafer-scale modules. InFO capacity has expanded alongside CoWoS but serves a largely non-overlapping customer set.

FO-WLP (Fan-Out Wafer-Level Packaging) is the broader category of fan-out packaging performed at OSATs — ASE, Amkor, and JCET are the primary providers. FO-WLP serves mobile SoCs, RF front-end modules, automotive radar chips, and a wide range of consumer applications. FOPLP (Fan-Out Panel-Level Packaging) moves the same technology from circular wafers to rectangular panels, increasing throughput and reducing cost per unit. FOPLP has been a long-promised cost disruption that is now entering real production at OSATs and at foundry captive lines.

Substrates & Interposers

The substrate and interposer layer sits between the die (or dies) and the board. Advanced packaging depends on four substrate/interposer technologies, each with its own supply chain concentration.

FCBGA substrate supply has been a persistent bottleneck. Advanced substrate lead times extended to 40+ weeks during the AI buildout; capacity has been expanding but remains capital-intensive with multi-year build cycles. Ajinomoto's ABF laminate is the canonical single-supplier dependency in this layer: ABF is used in essentially every high-pin-count FCBGA substrate worldwide, making Ajinomoto's production capacity a direct constraint on advanced packaging output. See Substrates & Interposers for deeper coverage.

Hybrid Bonding

Hybrid bonding is the enabling technology for the next generation of 3D integration. Conventional 3D stacking uses micro-bumps — tiny solder balls between TSV pads — which limits pitch to roughly 20-40 µm and introduces thermal resistance at each bump. Hybrid bonding eliminates the bumps entirely: the two die surfaces are planarized to atomic flatness, brought into contact, and direct copper-to-copper metallic bonds form at the contact points while the surrounding dielectric bonds form between oxide surfaces. The result is sub-10 µm pitch, no solder, and dramatically lower thermal and electrical resistance at the interconnect.

Hybrid bonding equipment supply is highly concentrated. BESI developed the first commercial hybrid bonder and now supplies the technology in partnership with Applied Materials, which brings wafer-processing know-how. Tokyo Electron has competing hybrid bonder offerings. The total global installed base remains small, and every new AI accelerator generation requiring hybrid bonding for HBM4 or for die-on-die stacking (TSMC SoIC, Intel Foveros Direct) competes for the same limited tool supply. Hybrid bonding tool availability is one of the tightest choke points in the next-generation advanced packaging supply chain.

Captive vs. OSAT for Advanced Packaging

A decade ago, packaging was almost universally outsourced to OSATs. Advanced packaging has inverted this. CoWoS runs at TSMC captive lines in Taiwan; InFO runs at TSMC captive. EMIB and Foveros run at Intel captive packaging plants in New Mexico, Oregon, and Arizona. I-Cube and SAINT run at Samsung Foundry captive. SK hynix packages its own HBM stacks. The strategic reason is process co-optimization: for advanced packaging, the interposer or bridge is fabricated at the same foundry that makes the logic die, and the packaging process is tuned in lockstep with the front-end process. Handing this off to an external OSAT would break the co-optimization loop.

OSATs still play a major role in advanced packaging, but at a different tier: FO-WLP and FOPLP for mobile and RF applications, substrate-based 2.5D for applications that don't require silicon-interposer bandwidth, and high-volume fan-out for consumer SoCs. ASE, Amkor, and JCET are all investing aggressively in advanced packaging capacity, but they compete for the mid-tier of the market rather than the leading-edge AI accelerator tier where TSMC CoWoS dominates. Amkor's Arizona buildout under CHIPS Act support is the flagship Western advanced-packaging reshoring project.

Advanced Packaging Bottlenecks

Strategic & Geopolitical Framing

Advanced packaging has moved from being a back-end assembly concern to being treated as a national security and industrial policy priority, alongside leading-edge fab capacity. The reasoning is structural: an AI accelerator cannot ship without CoWoS, CoWoS production is concentrated in Taiwan, and there is no Western alternative at equivalent scale through the end of this decade. The US CHIPS Act has included advanced packaging in its funding and incentive targets. The European Chips Act similarly treats packaging as strategic. The TSMC Arizona buildout includes advanced packaging alongside front-end fabrication. Amkor's Arizona facility is the flagship Western reshoring project specifically for packaging.

The Terafab vertical integration thesis is a related response: for strategic programs where packaging, front-end, and design must co-optimize, in-house integration becomes the only viable answer. The industry expectation over the next decade is that advanced packaging capacity will remain a binding constraint even as new capacity comes online, and that the concentration story will shift rather than dissolve — from TSMC's geographic concentration toward a broader but still-concentrated global landscape.

Related Coverage

Parent: Back-End Assembly & Packaging Hub

Sibling sub-hub: Back-End Assembly

Architecture children: CoWoS · InFO · Foveros · EMIB · I-Cube · FO-WLP · 3D IC · SiP · 2.5D · Advanced Packaging Detail · Comparison Matrix

Advanced interconnect & hybrid bonding: Advanced Interconnects · 3D IC Hybrid Bonding

Substrates and packaging test: Substrates & Interposers · Advanced Packaging Test

Cross-pillar dependencies: HBM · AI Accelerators (CoWoS consumers) · Module Integration · Tesla Terafab · Bottleneck Atlas