CoWoS Packaging

CoWoS — Chip-on-Wafer-on-Substrate — is TSMC's 2.5D advanced packaging architecture and the most strategically significant advanced packaging technology in the semiconductor industry. Every NVIDIA H100, H200, B100, B200, GB200, and Rubin generation GPU ships on CoWoS. Every AMD MI300 and MI400 series AI accelerator ships on CoWoS. Every major hyperscaler custom AI silicon program — Google TPU, Amazon Trainium and Inferentia, Microsoft Maia — depends on CoWoS capacity allocation. The Tesla AI5 chip is among the incoming CoWoS customers at TSMC Arizona. CoWoS capacity is the single binding global supply constraint on the AI accelerator market. TSMC has roughly doubled CoWoS capacity annually since 2023, and demand continues to outrun supply.

CoWoS exists in three variants that share the architectural pattern but differ in the carrier technology underneath the dies: CoWoS-S uses a full silicon interposer (the classic implementation, highest bandwidth, highest cost); CoWoS-R uses an RDL-based interposer (lower bandwidth, lower cost); CoWoS-L uses local silicon interconnect bridges embedded in an organic carrier (hybrid approach between CoWoS-S and a bridge architecture like EMIB). All three variants place a logic die plus multiple HBM stacks side-by-side on the carrier and route the inter-die signals through it. Production of the carrier and the CoWoS assembly runs captive at TSMC — there is no merchant market for CoWoS interposers or for CoWoS-assembled modules.

The Physical Structure

The name is literal. Chip-on-wafer-on-substrate describes the three-layer stack of the completed module: multiple chips (a logic die and two or more HBM stacks) sit on a silicon wafer (the interposer, which itself has been fabricated with TSVs and back-end-of-line routing at TSMC); that wafer sits on a substrate (an organic FCBGA laminate that provides the connection to the board).

The assembly sequence is "chip on wafer" first (logic die and HBM stacks bonded to the interposer while the interposer is still part of an intact wafer), then the populated interposer wafer is thinned, diced, and mounted on the organic substrate. Underfill, encapsulation, and lid attach complete the module. The full CoWoS assembly runs at TSMC advanced packaging sites in Taiwan, with additional capacity ramping at TSMC Arizona.

The Three Variants

CoWoS variants are not three competing products — they are three points on a cost/performance curve, each serving a different segment of the advanced packaging customer base. TSMC allocates each customer to the variant that matches the customer's bandwidth requirement, interposer area, and cost target.

CoWoS-S is the incumbent and the volume workhorse — it is what "CoWoS capacity" references mean when the industry discusses the binding AI accelerator constraint. CoWoS-L is the growing variant for customers who need CoWoS-level integration without the full silicon-interposer cost, and it eases the pressure on CoWoS-S capacity by diverting customers who don't require the top bandwidth tier. CoWoS-R serves mid-performance customers and specialty applications.

Interposer area is a critical dimension. Early CoWoS-S modules fit within a single photolithography reticle field (roughly 858 mm² at TSMC's reticle limit). Current-generation AI accelerator modules have pushed interposer area well beyond the reticle limit, requiring stitched or reticle-extending interposer fabrication — a technical capability that TSMC has continued to expand generation over generation. Modules with interposer areas of 3×, 4×, and larger than the reticle limit are in production for flagship AI accelerators, and beyond-reticle interposer capability is one of the competitive differentiators of CoWoS-S versus any potential alternative architecture.

The HBM Integration Story

CoWoS exists primarily to integrate HBM stacks with logic dies at bandwidth impossible through any organic substrate. A modern AI accelerator package carries a logic die (the compute silicon) plus 2, 4, 6, 8, or 12+ HBM stacks arranged around it. Each HBM stack carries over 1,000 signal pins to the logic die; the aggregate die-to-HBM connection count runs into the tens of thousands across a full module.

The silicon interposer (CoWoS-S) or its variant (CoWoS-R, CoWoS-L) provides the routing layer that carries those signals between the HBM stacks and the logic die at the pitch and density required. The interposer's TSVs carry vertical paths from the HBM and logic top surfaces down through to the substrate below; the BEOL routing on the interposer top handles the horizontal die-to-die traffic. See Advanced Interconnects for the TSV and micro-bump detail and HBM for the memory-side view of the integration.

HBM generation and CoWoS generation are tightly coupled in the roadmap. CoWoS has evolved alongside HBM2, HBM2E, HBM3, HBM3E, and now HBM4. HBM4 introduces hybrid bonding at the die-to-die interface inside the HBM stack itself, which increases the stack height flexibility and thermal performance — but the HBM stack still connects to the CoWoS interposer through micro-bumps at the 40–55 µm pitch interface. The die-to-die-on-interposer interface has not yet migrated to hybrid bonding broadly; that transition is expected later this decade.

Customer Applications

CoWoS customers are a who's-who of the AI, HPC, and hyperscaler silicon landscape. The list below is representative rather than exhaustive; every major AI accelerator program in volume production globally either uses CoWoS today or has announced a roadmap on it.

Capacity as Binding Constraint

CoWoS capacity has been the single most-watched strategic metric in semiconductor manufacturing since the AI buildout accelerated in 2023. TSMC reports CoWoS capacity expansion at each earnings cycle; every major fabless AI accelerator customer references CoWoS allocation as a determinant of their shipment ramp; every hyperscaler deploying AI infrastructure at scale monitors CoWoS output. The binding constraint is structural: CoWoS is near-sole-source at TSMC, the interposer fabrication is capital-intensive and cycle-long, and the demand trajectory has outrun every capacity expansion so far.

TSMC has doubled CoWoS capacity annually since 2023 and has guided continued aggressive expansion through the remainder of this decade. Capacity sits at TSMC advanced packaging facilities in Taiwan, with Arizona capacity ramping as part of the CHIPS Act-era fab and advanced packaging buildout. Samsung Foundry's I-Cube is the closest competitive architecture but runs at much smaller scale and without the customer breadth of CoWoS; Intel's EMIB serves a different segment; no merchant OSAT operates a CoWoS-equivalent capacity. The closest structural peer on the horizon is the hybrid bonding 3D stacking path (SoIC, Foveros Direct) that will partially offload die-on-die integration from CoWoS as chiplet architectures mature.

Supply Chain Dependencies

CoWoS assembly depends on multiple upstream supply chains, each with its own concentration story.

Geographic Footprint

CoWoS production concentrates at TSMC advanced packaging facilities in Taiwan, with Arizona capacity ramping as part of the TSMC U.S. buildout under CHIPS Act support. TSMC's Arizona advanced packaging capacity serves the captive logic-die output from TSMC Arizona fabs and is allocated to specific customer programs — Tesla AI5 among them — rather than serving the broad CoWoS customer base. Japan is part of the supporting ecosystem through substrate and material supply but does not host CoWoS assembly.

The geographic concentration at Taiwan has driven the industrial policy response visible in the CHIPS Act and in parallel European, Japanese, and Korean initiatives. CoWoS, alongside leading-edge fabrication and HBM production, is treated as a national-security-relevant capacity bottleneck because the entire AI accelerator ship flow depends on it. The trajectory over the next decade is broader geographic distribution of CoWoS and CoWoS-equivalent capacity, with Taiwan remaining the center of gravity.

Market Outlook

CoWoS demand is expected to grow faster than any other advanced packaging category through the end of this decade, driven by AI accelerator production ramp, HBM-per-module count growth (each new AI accelerator generation carries more HBM stacks, which requires larger interposers and more CoWoS area per unit), hyperscaler custom silicon programs expanding, and the emergence of new AI accelerator entrants (custom-silicon programs at multiple hyperscalers, enterprise AI accelerators, specialty AI silicon). TSMC's capacity expansion trajectory has consistently underestimated the demand, and the expectation through the decade is that CoWoS will remain a binding constraint.

The competitive landscape is stable at the top tier. I-Cube (Samsung) and EMIB (Intel) serve different segments; neither is a direct volume substitute for CoWoS at the flagship AI accelerator tier. The long-term architectural competition comes from 3D hybrid bonding (SoIC, Foveros Direct, next-generation SAINT) which will absorb some of the functions CoWoS currently provides — particularly die-on-die stacking for logic — while leaving HBM-plus-logic 2.5D integration as CoWoS territory for the foreseeable future. Beyond-reticle interposer capability and the transition to hybrid bonding at the HBM-to-interposer interface are the technical frontiers to watch.

Related Coverage

Parent: Advanced Packaging

Peer 2.5D architectures: EMIB · I-Cube

Peer 3D architectures (chiplet complement): Foveros · 3D IC (incl. SoIC)

Foundation layers: Substrates & Interposers (silicon interposer detail) · Advanced Interconnects (TSV + micro-bump)

Cross-architecture reference: Comparison Matrix

Cross-pillar dependencies: AI Accelerators (CoWoS consumers) · HBM (integrated memory stacks) · Bottleneck Atlas (CoWoS as binding constraint) · Tesla Terafab (AI5 Arizona allocation)