Compute & Logic Chips

Compute and logic semiconductors execute instructions, run inference, switch packets, control actuators, and implement programmable logic across every tier of the digital economy. The cluster spans a wider process node range than any other chip category — from sub-2nm leading-edge CMOS for AI training GPUs to 180nm mature node for automotive safety MCUs — and contains two supply chain populations with almost nothing in common except their silicon substrate.

The leading-edge population (CPUs, GPUs, AI accelerators, inference SoCs, advanced ASICs) is defined by TSMC concentration at N3/N5, CoWoS advanced packaging as a second constraint layer, and EDA lock-in through Synopsys and Cadence. The mature-node population (embedded MCUs, security silicon) is defined by 200mm fab capacity, AEC-Q100 qualification lock-in, and the $2 Chip Paradox dynamic where a low-cost device commands structural supply chain rigidity far beyond its unit price. FPGAs span both populations depending on device tier. Memory and storage — DRAM, NAND, HBM — are a peer cluster with their own supply chain character and are covered separately under Memory & Storage.

Compute & Logic Device Families — Products & Process

Deployment & Supply Chain Risk by Device Type

Two Supply Chain Populations

Leading-edge CMOS population. CPUs, GPUs, AI accelerators, inference SoCs, advanced ASICs, and high-end FPGAs all compete for TSMC N3/N5 wafer allocation. This is a zero-sum pool: a surge in AI GPU demand — as occurred in 2023–2024 — directly compresses wafer availability for server CPUs, networking ASICs, and high-end FPGAs. CoWoS advanced packaging at TSMC adds a second constraint layer that is physically separate from wafer starts; it was the binding bottleneck on NVIDIA GPU shipments during the Hopper generation ramp. EDA lock-in through Synopsys and Cadence is a third structural dependency — every fabless company designing at N3/N5 requires both tools, creating a duopoly chokepoint upstream of the foundry.

Mature-node population. Embedded MCUs, security silicon, and low-power FPGAs operate at 28–180nm on 200mm fabs. Their supply chain risk is not process density — it is qualification lock-in. AEC-Q100, ISO 26262, and CC EAL security certifications create 12–24 month re-qualification cycles that make device substitution nearly impossible within a platform generation. The $2 Chip Paradox — where a sub-$5 MCU halts a $55,000 vehicle — is the defining editorial thesis for this population. Mature-node capacity investment has historically lagged leading-edge investment, creating periodic shortage events that expose the qualification lock-in problem acutely.

The AI GPU Stacked Bottleneck

The NVIDIA H100/H200/B200 supply chain is the most structurally constrained in the Compute & Logic cluster — and arguably in all of semiconductors. Three independent constraints apply simultaneously: TSMC N4/N3 wafer starts for the GPU die, CoWoS packaging capacity at TSMC to integrate the GPU die with HBM stacks on a silicon interposer, and SK Hynix HBM3E supply for the memory stacks themselves. Each constraint is on a different physical resource with a different expansion timeline. Relieving one does not relieve the others. This stacked bottleneck structure means that GPU supply cannot be increased by addressing any single constraint — all three must expand in parallel, and all three are on multi-year lead times.

Related Coverage

Memory & Storage — Peer Cluster | AI Inference & Edge Compute SoCs | Mature Node MCUs — The $2 Chip Paradox | RF & Networking | Semiconductor Bottleneck Atlas | CoWoS Advanced Packaging | NVIDIA Spotlight | Apple Silicon Spotlight

Cross-Network — ElectronsX Demand Side

Every electrified vehicle, autonomous platform, and humanoid robot contains devices from both supply chain populations simultaneously — a leading-edge inference SoC for perception and decision-making, and dozens of mature-node MCUs for actuator control, safety monitoring, and sensor interfacing. The AI training infrastructure that generates the models deployed in those vehicles and robots depends entirely on the leading-edge GPU and accelerator supply chain covered here.

EX: ADAS/AV Compute Architecture | EX: EV Semiconductor Dependencies | EX: Humanoid Robots | EX: Supply Chain Convergence Map