SemiconductorX > Materials & IP > Silicon Wafer Production > Crystal Growing
Semiconductor Crystal Growing
Crystal growing converts polysilicon feedstock into a single-crystal ingot -- the boule -- from which wafers are sliced. The method used determines the wafer's purity ceiling, maximum diameter, oxygen content, and cost structure. Silicon uses two methods: Czochralski (CZ) for the vast majority of production, and Float Zone (FZ) for the highest-purity applications. Silicon carbide uses a fundamentally different technique -- Physical Vapor Transport (PVT) -- operating at roughly twice the temperature of silicon growth and constrained by physics that do not apply to silicon.
Growth Method Comparison
| Parameter | Czochralski (CZ) | Float Zone (FZ) | Physical Vapor Transport (PVT) -- SiC |
|---|---|---|---|
| Feedstock | Polysilicon chunks/granules in quartz crucible | Polysilicon rod; no crucible contact | SiC source powder sublimated by RF induction |
| Growth temperature | ~1,420°C (silicon melting point) | ~1,420°C; localized RF molten zone | 2,100-2,400°C |
| Growth rate | ~1-2 mm/min pull rate | ~3-5 mm/min | 0.3-0.5 mm/hour -- the primary production bottleneck |
| Oxygen content | ~1018 atoms/cm³ -- inherent from quartz crucible dissolution | <1015 atoms/cm³ -- no crucible contact | Not applicable; SiC crystal, not silicon |
| Purity | High; oxygen and some metallic contamination managed but present | Highest purity silicon available; sub-ppb metallic impurities | SiC-specific purity; micropipe and polytype defect density is the key metric |
| Max commercial diameter | 300mm (12-inch) in volume production; 450mm R&D only | 200mm (8-inch) -- physics limit; melt zone instability prevents scaling | 150mm (6-inch) in volume production; 200mm in qualification |
| Energy intensity | High; furnace runs continuously for several days per boule; graphite resistance heaters above 1,420°C | Moderate; RF-heated zone, shorter cycle | Very high; 2,100-2,400°C sustained for weeks per boule |
| Primary applications | Logic, memory, foundry -- all mainstream silicon wafer production | Power devices, RF, high-resistivity applications requiring ultra-low oxygen | SiC power devices (MOSFETs, Schottky diodes) for EV inverters, industrial drives, solar |
| Market share | ~90%+ of silicon wafer production by volume | ~5-10%; niche, premium applications | 100% of SiC substrate production; growing rapidly with EV and industrial power demand |
Czochralski Process: Oxygen & Defect Management
The quartz (SiO2) crucible is an intrinsic oxygen source in CZ growth. As silicon melts, the crucible walls dissolve into the melt, incorporating oxygen at concentrations of approximately 1018 atoms/cm³ in the grown crystal. This is not simply a contamination problem to be eliminated -- oxygen in CZ silicon plays a dual role. At controlled concentrations, interstitial oxygen strengthens the wafer mechanically by pinning dislocations, and intentionally precipitated oxygen acts as an internal gettering site that traps metallic impurities away from active device regions. However, oxygen also forms electrically active defects in combination with dopants such as boron, and uncontrolled precipitation degrades minority carrier lifetime.
Oxygen concentration is managed through crucible rotation speed, crystal pull rate, argon gas flow (which carries evaporated SiO from the melt surface), and magnetic field application in Magnetic CZ (MCZ) systems. MCZ applies a static or transverse magnetic field to dampen melt convection, reducing oxygen transport from the crucible wall to the crystal interface -- particularly important for advanced node logic and memory wafers where tight oxygen specification windows are required.
SiC Crystal Growing: Physical Vapor Transport (PVT)
SiC cannot be grown from a melt -- it sublimes rather than melts at atmospheric pressure, and the melting point exceeds 2,700°C at extreme pressures. PVT (also called the Lely method in modified form) sublimates SiC source powder at 2,100-2,400°C using RF induction heating. The vapor phase -- carrying Si, Si2C, and SiC2 species -- re-condenses onto a cooler SiC seed crystal at the top of a graphite crucible, building up the boule layer by layer. Growth rates of 0.3-0.5 mm per hour mean a standard SiC boule requires weeks of continuous furnace operation, compared with days for a silicon CZ boule.
The slow growth rate is a hard physical constraint, not a process engineering shortcoming. It sets the economic floor for SiC substrate costs and is the primary reason SiC wafers cost roughly 5-10x more than equivalent-diameter silicon wafers. Defect control -- particularly micropipes (hollow-core screw dislocations), basal plane dislocations, and polytype inclusions -- is the key quality metric. Commercial-grade SiC has progressed from micropipe densities of hundreds per cm² to near-zero micropipe specification for leading suppliers, enabling the high-voltage blocking and switching performance required for EV inverters and industrial power applications.
Silicon Wafer Size Market
| Wafer Size | Market Share (by value) | Primary Applications | Notes |
|---|---|---|---|
| 300mm (12-inch) | ~75% of total silicon wafer market value | Advanced logic, DRAM, NAND flash, leading-edge foundry | Dominant for advanced nodes; ~30-40% cost-per-chip advantage over 200mm; all Tier-1 logic and memory fabs |
| 200mm (8-inch) | ~20% by value | Analog, mixed-signal, power discretes, MEMS, sensors, mature node MCUs | Persistent demand from automotive and industrial; constrained capacity from lack of new 200mm fab investment; see Mature Node MCU / $2 Chip Paradox |
| 150mm and below | ~5% by value | Compound semiconductors (GaAs, InP), specialty power, SiC (transitioning from 150mm to 200mm) | Declining for silicon; SiC currently at 150mm in volume production with 200mm qualification underway |
| 450mm (18-inch) | R&D only; no commercial production | Future advanced logic and memory if industry-wide investment materializes | Requires complete new equipment ecosystem; economics require near-simultaneous commitment from TSMC, Samsung, Intel, and tool suppliers; no firm commercial timeline |
Silicon Wafer Supplier Landscape
The silicon wafer market is one of the most concentrated in the semiconductor supply chain. Five producers hold approximately 85-89% of global 300mm wafer capacity, with Japan dominant at the top two positions. Customer qualification cycles of 2-4 years and proprietary crystal-pulling expertise create high barriers to entry -- no new entrant has successfully broken into Tier-1 advanced silicon wafer supply in decades.
| Supplier | HQ | Est. 300mm Share | Key Notes |
|---|---|---|---|
| Shin-Etsu Chemical | Japan | ~27% | #1 global; Japan and Singapore plants; CHIPS Act-supported 300mm expansion in Sherman, Texas underway |
| Sumco | Japan | ~24% | #2 global; Japan primary; released high-purity low-defect 300mm wafers for advanced DRAM and GPU |
| GlobalWafers | Taiwan | ~17% | #3 global; acquired Siltronic (Germany) assets; specialty 300mm with built-in epi for RF and power ICs |
| Siltronic | Germany | ~12% | European supply anchor; 300mm SOI wafers for embedded sensors; GlobalWafers acquisition attempt blocked by EU regulators |
| SK Siltron | South Korea | ~9% | Samsung subsidiary; primary supplier into Samsung memory and foundry; also produces SiC epiwafers via acquired Dupont SiC unit |
Shin-Etsu and Sumco together control approximately 50% of global 300mm wafer supply. Japan's combined position across the top two suppliers makes Japanese wafer production a geographic concentration risk analogous to ASML's position in EUV lithography -- a single-country chokepoint for the upstream silicon supply chain.
SiC Substrate Suppliers
SiC crystal growing is addressed in detail on the SiC Substrates & Epiwafers page. Key producers include Wolfspeed (US, #1 by installed capacity), SICC and TanKeBlue (China, rapidly scaling), Onsemi/GTAT (US, captive supply), Coherent (US, formerly II-VI), SiCrystal (Germany, a Rohm subsidiary), and SK Siltron (Korea). The 150mm to 200mm wafer transition is the defining near-term event in SiC supply chain development.
Supply Chain Outlook
Silicon wafer supply is structurally secure for mature nodes but capacity-constrained for 300mm advanced node production, where qualification timelines and capital intensity limit new entrant viability. Japan's concentration at positions one and two creates a supply chain dependency without a near-term structural alternative -- Shin-Etsu's Texas expansion and GlobalWafers' capacity growth are diversifying geography but not changing the fundamental oligopoly. SiC substrate supply remains the tighter constraint: PVT growth physics set a hard ceiling on how fast SiC boule production can scale, and the 200mm transition requires new equipment qualifications across the entire substrate-to-device supply chain.
Related Coverage
Silicon Wafer Production Overview | Materials & IP Hub | Silicon Ingots | Wafer Slicing | Wafer Polishing & CMP | Epitaxy & SOI Wafers | SiC Substrates & Epiwafers | Quartzite Mining & Polysilicon | SiC Nine-Market Convergence Spotlight | Mature Node MCUs / $2 Chip Paradox | Bottleneck Atlas