Specialty Silicon Wafers — Epi, SOI & Float Zone

Epitaxy deposits a thin single-crystal semiconductor layer on a substrate wafer, precisely matching the substrate's crystal orientation. The grown layer -- the epitaxial (epi) layer -- can be doped independently of the substrate, have a different composition, or provide a cleaner starting surface than the bulk wafer below. Epi wafers are a value-added deliverable: the wafer supplier performs the epitaxy step before shipping, allowing the fab to skip in-house deposition or to receive a substrate optimized for specific device requirements. Silicon-on-insulator (SOI) wafers are an engineered substrate variant where a buried oxide layer separates a thin silicon device layer from the handle wafer, enabling full dielectric isolation of active devices.

Silicon Epitaxy: CVD Process

Silicon epi is grown by chemical vapor deposition (CVD) at 1,050-1,200°C in a reactor chamber where silicon-containing gas decomposes on the heated substrate surface, depositing a crystalline silicon layer that continues the substrate lattice. Three precursor gases are used depending on deposition temperature and growth rate requirements.

Precursor	Formula	Deposition Temp	Growth Rate	Notes
Trichlorosilane (TCS)	SiHCl3	1,100-1,200°C	1-3 µm/min	Most common; high purity; same intermediate used in Siemens polysilicon process; favorable economics at scale
Dichlorosilane (DCS)	SiH2Cl2	1,000-1,100°C	0.1-0.5 µm/min	Lower temperature enables epi growth on patterned substrates without autodoping; preferred for thin epi on advanced CMOS substrates
Silane (SiH4)	SiH4	900-1,050°C	0.05-0.3 µm/min	Lowest deposition temperature; used for ultra-thin epi and SiGe heterostructures; pyrophoric -- requires strict safety handling

Dopants are introduced by adding boron (from diborane, B2H6) for p-type or phosphorus/arsenic (from phosphine PH3 or arsine AsH3) for n-type during growth, enabling precise doping profiles independent of the substrate. The reactor runs in hydrogen carrier gas at reduced pressure. After growth, the reactor undergoes an HCl etch-clean cycle to remove silicon deposits from chamber walls between wafer runs. Barrel, pancake, and single-wafer (rotating susceptor) reactor geometries are all in use; single-wafer reactors dominate at 300mm for their superior thickness and resistivity uniformity control.

Epi Reactor Equipment

Silicon epi reactors for wafer production are supplied by a concentrated equipment market. Applied Materials (US) dominates with its Centura Epi platform, the standard single-wafer reactor for 200mm and 300mm production. ASM International (Netherlands) supplies the Epsilon single-wafer reactor series, competitive particularly for advanced thin epi and SiGe applications. Kokusai Electric (Japan, formerly Hitachi Kokusai) supplies batch epitaxial reactors used at some mature-node producers. The choice between single-wafer and batch reactors involves a tradeoff: single-wafer delivers tighter uniformity and faster recipe changeover; batch delivers higher throughput for simpler, high-volume epi runs.

Epi Layer Types & Applications

Epi Type	Typical Thickness	Doping	Primary Application	Notes
Standard p-on-p+ epi	2-8 µm	Lightly boron-doped epi on heavily doped p+ substrate	Mainstream CMOS logic and DRAM; reduces latch-up risk vs bulk; provides cleaner device layer	Most widely used epi configuration; heavy substrate acts as a gettering sink for metallic impurities; standard deliverable from Shin-Etsu, Sumco, Siltronic
Doped epi (power/analog)	5-100 µm	n-type or p-type; precisely graded	Power MOSFETs, IGBTs, bipolar transistors, analog; epitaxial drift layer determines device breakdown voltage	Thick epi for high-voltage devices (>100V); resistivity and thickness uniformity are critical specifications; delivered by Siltronic, GlobalWafers, SK Siltron
Thin epi (<1 µm)	10-500 nm	Undoped or lightly doped	Advanced CMOS channel layer; SiGe strained channel epi; FinFET fin material	Grown in-fab at TSMC, Samsung, Intel on pre-delivered polished or SOI substrates; not typically a pre-delivered wafer epi type except on engineered substrates from Soitec
SiGe epi	5-50 nm	p-type (boron) for channel; undoped for virtual substrate	Strained silicon channel in FinFET and gate-all-around; SiGe source/drain stressors; SiGe virtual substrates for strained silicon	Grown in-fab using SiH4 + GeH4; germanium content (typically 15-30%) determines strain magnitude; GeH4 sourcing exposed to Chinese germanium export controls
RF epi (high-resistivity Si)	2-5 µm	Very lightly doped; high resistivity substrate	RF-SOI switches and antenna tuners for smartphone front-end modules; reduces substrate loss at RF frequencies	Used on high-resistivity SOI; GlobalWafers specialty epi for RF-SOI; key for 5G front-end module supply chain

SOI Wafers: Structure & Technology

Silicon-on-insulator wafers replace the bulk silicon substrate with a layered structure: a thin silicon device layer, a buried oxide (BOX) layer of silicon dioxide, and a silicon handle wafer. Devices built in the silicon device layer are fully isolated from the handle wafer by the BOX, eliminating leakage currents through the substrate and enabling full dielectric isolation without junction isolation implants. The resulting benefits are lower off-state leakage (critical for low-power mobile devices), reduced parasitic capacitance (enabling RF performance), and simpler device isolation at advanced nodes.

Soitec's Smart Cut process is the dominant SOI manufacturing technology. A donor silicon wafer receives a hydrogen ion implant at a controlled depth (which will become the device layer thickness). The implanted surface is bonded to an oxidized handle wafer. Thermal annealing causes the hydrogen-implanted plane to fracture (cleave), leaving a thin silicon layer bonded to the handle. CMP smooths the transferred surface to device-quality roughness. The donor wafer is reclaimed and reused. Smart Cut can produce device layers from a few nanometers to several micrometers with uniformity of ±0.5nm across 300mm -- a specification that requires extraordinary process control at both the implant and CMP steps.

SOI Variants & Supplier Landscape

SOI Type	Device Layer	BOX Thickness	Primary Application	Key Supplier
FD-SOI (Fully Depleted)	5-12 nm	25 nm (thin BOX)	Low-power logic: STMicro 28nm FD-SOI, 22nm FD-SOI; GlobalFoundries 22FDX; body-biasing for dynamic Vt tuning	Soitec (FR) -- near-monopoly; Samsung also qualifies Soitec for its FD-SOI supply
RF-SOI	70-200 nm	100-200 nm	Smartphone RF switches, antenna tuners, LNA; reduces substrate loss at sub-6 GHz and mmWave	Soitec (FR) dominant; GlobalWafers also supplies RF-SOI variants
Photonics SOI	220 nm (standard silicon photonics)	2-3 µm (thick BOX for optical confinement)	Silicon photonics waveguides, modulators, photodetectors; datacenter optical transceivers	Soitec (FR); also SHIN-ETSU and GlobalWafers for some photonics SOI
Power SOI	0.5-100 µm	0.1-4 µm	Smart power ICs, automotive; dielectric isolation between high-voltage and low-voltage circuit sections	GlobalWafers, Shin-Etsu; Soitec for some power SOI variants

Soitec's Strategic Position

Soitec holds a near-monopoly on FD-SOI and RF-SOI wafer supply -- the two SOI types most critical to smartphone logic (FD-SOI at STMicroelectronics and GlobalFoundries) and RF front-end (RF-SOI at RFMD/Qorvo, Skyworks, and their foundry partners). This concentration is structurally similar to ASML's EUV scanner monopoly: the technology (Smart Cut) is proprietary, the qualification cycle is long, and no credible alternative at scale exists. Soitec's Bernin facility near Grenoble is the primary production site, with additional capacity in Singapore and plans aligned with European semiconductor policy. Any disruption to Soitec's production would cascade directly into FD-SOI foundry capacity at STMicro and GlobalFoundries 22FDX -- nodes that serve IoT, automotive, and wearables markets where low-power performance is the design objective.

Float Zone (FZ) Silicon Wafers

Float Zone silicon is grown by the FZ method (RF induction heating of a localized molten zone passed along a polysilicon rod, with no crucible contact) rather than by Czochralski pulling. The absence of a quartz crucible eliminates the primary oxygen contamination source in CZ growth, producing silicon with oxygen concentrations below 10¹⁵ atoms/cm³ -- more than three orders of magnitude lower than CZ silicon's ~10¹⁸ atoms/cm³. FZ silicon also achieves higher resistivity than CZ silicon because oxygen precipitation-related defects are absent and minority carrier lifetimes are substantially longer.

These properties make FZ silicon the substrate of choice for specific device categories where CZ silicon's oxygen content is disqualifying. High-voltage power devices (IGBTs, power diodes at 3,300V and above) require the long minority carrier lifetime that FZ silicon provides to achieve the forward voltage drop and switching characteristics the design targets. RF and microwave devices requiring extremely high resistivity substrates (above 10,000 Ω·cm) use FZ silicon because CZ silicon cannot reach comparable resistivity levels. Radiation detectors for high-energy physics experiments (CERN LHC/HL-LHC) specify FZ silicon because oxygen in CZ silicon forms electrically active defect clusters under high radiation doses, degrading detector resolution -- FZ's near-zero oxygen baseline provides better radiation hardness before the oxygen-vacancy trapping mechanism degrades performance.

Parameter	FZ Silicon	CZ Silicon	Significance
Oxygen content	<10¹⁵ atoms/cm³	~10¹⁸ atoms/cm³	CZ oxygen degrades minority carrier lifetime and forms defect clusters under radiation; FZ avoids both
Resistivity range	Up to >30,000 Ω·cm	Typically <5,000 Ω·cm (oxygen-limited)	Ultra-high resistivity required for RF substrates and radiation detectors
Minority carrier lifetime	Milliseconds range	Microseconds to milliseconds (oxygen-dependent)	Long lifetime essential for high-voltage bipolar and IGBT power devices
Max diameter	200mm (8-inch) -- physics limit from melt zone instability	300mm in volume; 450mm R&D	FZ cannot scale to 300mm; power and detector device fabs using FZ are limited to 200mm or below
Cost vs CZ	2-5x premium at equivalent diameter	Baseline	Cost premium justified only where FZ's low-oxygen properties are device-critical; not used for mainstream logic or memory
Primary applications	High-voltage IGBTs/diodes (>3.3kV), RF high-resistivity substrates, particle physics radiation detectors, neutron transmutation doped (NTD) silicon for power	All mainstream logic, memory, analog, CMOS power	FZ serves niche but technically irreplaceable applications where CZ cannot meet specification

Siltronic (Germany) is the primary global supplier of FZ silicon wafers and holds a strong market position in this niche -- a natural extension of its Wacker Group origins in high-purity silicon chemistry. Shin-Etsu Chemical and Sumco also produce FZ wafers, primarily for their Japanese power device customer base. The FZ wafer market is small in volume compared to CZ but commands significant price premiums. Neutron transmutation doping (NTD) is a related process used with FZ silicon: the wafer is irradiated in a nuclear reactor, converting silicon-30 to phosphorus-31 via neutron capture, producing a uniquely uniform n-type doping profile across the entire wafer volume -- a uniformity level impossible to achieve by conventional diffusion or ion implant, required for the highest-voltage power thyristors and IGBTs.

Supply Chain Outlook

Standard silicon epi wafer supply is well-handled by all five major silicon wafer suppliers and is not a concentration risk. SOI risk concentrates at Soitec: its FD-SOI and RF-SOI near-monopoly is a structural dependency for the specific foundry nodes (STMicro FD-SOI, GlobalFoundries 22FDX, RF-SOI for smartphone front-end) that have standardized on these substrates. SiGe epi grown in-fab carries a secondary germanium export control exposure via GeH4 precursor -- a risk that intensifies as SiGe channels become standard in FinFET and gate-all-around device architectures. Silicon photonics SOI demand will tighten as AI datacenter 400G/800G/1.6T transceiver volumes scale. FZ silicon supply is stable and adequate for its niche markets, with Siltronic as the primary Western supplier; the 200mm diameter ceiling is a structural constraint that cannot be engineered away, keeping FZ confined to applications that can economically accept smaller wafer sizes.

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Epi, SOI & Float Zone Wafers