ASICs

Application-Specific Integrated Circuits trade programmability for efficiency. Logic and interconnect are fixed at tape-out — the chip does exactly one thing, does it at maximum transistor efficiency, and cannot be reprogrammed. This makes ASICs the highest-performance, lowest-power option for any workload that is stable enough at volume to justify the non-recurring engineering cost of custom silicon design. At advanced nodes, that NRE cost is $300–500 million at 5nm and rising — which concentrates ASIC design activity at hyperscalers, established networking companies, and large OEMs that can amortize NRE across sufficient volume.

The ASIC market divides cleanly into merchant ASICs (Broadcom and Marvell selling networking silicon to anyone who will buy) and captive ASICs (Google, AWS, Microsoft, Meta, Apple, Tesla designing chips exclusively for their own deployment). Both depend on TSMC at advanced nodes, both use the same Synopsys/Cadence EDA toolchain, and both compete for the same CoWoS packaging capacity. The structural difference is that merchant ASIC supply can be tracked through public revenues; captive ASIC wafer consumption is invisible to the market but draws from the same constrained foundry pool.

ASIC Families — Products & Process

Deployment & Supply Chain Risk

ASIC NRE Economics & the Build vs. Buy Decision

Custom ASIC design at advanced nodes is one of the highest-NRE activities in engineering. A full tape-out at TSMC N5 — including EDA tool licensing, IP core licensing (SerDes, PCIe, DDR, security), mask set costs, and verification engineering time — costs $300–500 million and takes 18–24 months from design start to first silicon. At N3, the cost escalates further. This economics profile concentrates ASIC development at companies with either the volume to amortize NRE (hyperscalers with millions of unit deployments) or the revenue to fund it (Broadcom and Marvell with large merchant ASIC businesses).

The decision framework is straightforward: ASICs win when workloads are stable, volumes are high, and the performance-per-watt improvement over GPU or FPGA alternatives generates enough TCO savings to justify NRE. They lose when algorithms change rapidly (making fixed function logic a liability), volumes are modest (making NRE non-recoverable), or time-to-market pressure exceeds the 18–24 month ASIC design cycle. FPGAs prototype the function; ASICs productize it at scale.

Supply Chain Bottlenecks

Related Coverage

Compute & Logic Hub | GPUs | AI Accelerators | FPGAs | RF & Networking | EDA Supply Chain | PDK & Foundry Ecosystem | Semiconductor Bottleneck Atlas

Cross-Network — ElectronsX Demand Side

Ambarella CV3-AD and NVIDIA DRIVE Thor compete for the same automotive ADAS domain controller design win — that design win locks in ASIC supply chain for the vehicle's production lifetime. Hyperscaler AI training ASICs (TPU, Trainium, Maia) are the infrastructure generating the models deployed in EVs, AVs, and robots. Qualcomm's modem ASIC near-monopoly means every connected vehicle and smart infrastructure node with 5G telematics depends on Qualcomm supply continuity.

EX: ADAS/AV Compute Architecture | EX: EV Semiconductor Dependencies | EX: Supply Chain Convergence Map