SemiconductorX > Fab & Assembly > Back-End Assembly & Packaging > Advanced Packaging > InFO
InFO (Integrated Fan-Out) Packaging
InFO — Integrated Fan-Out — is TSMC's proprietary fan-out wafer-level packaging architecture and the mobile-and-consumer counterpart to CoWoS. Where CoWoS addresses the AI accelerator market with a silicon interposer carrying HBM-plus-logic at extreme bandwidth, InFO addresses the mobile SoC market with a thin, high-density, low-parasitic package that eliminates the silicon interposer entirely. Apple's A-series and M-series system-on-chips — across iPhone, iPad, and Mac products — run on InFO. MediaTek, Qualcomm (in select products), and a growing base of other mobile and consumer fabless customers use InFO variants for their flagship silicon.
The fan-out concept is structurally different from both traditional flip-chip and silicon-interposer 2.5D. Rather than mounting the die on a substrate (flip-chip) or on a silicon interposer (CoWoS), InFO embeds the die in a reconstituted wafer of epoxy molding compound and routes its I/O outward through redistribution layers (RDL) built on top of the reconstituted wafer. The RDL routing "fans out" the die's bump pattern from the tight pitch of the die surface to the coarser pitch required for board-level BGA connections. The result is a very thin package (no substrate underneath the RDL), very short signal paths from die to package terminal, and very high interconnect density without the cost of a silicon interposer.
InFO is TSMC-captive — the architecture and its variants are produced at TSMC fan-out facilities in Taiwan. The broader fan-out ecosystem at OSATs (ASE, Amkor, JCET) uses parallel FO-WLP technology covered at FO-WLP. The two share the fan-out concept but differ in process variants, customer base, and performance tier: InFO is the foundry-captive high-performance tier; OSAT FO-WLP is the broader mobile-and-consumer volume tier.
The Fan-Out Construction
InFO construction runs as a five-stage sequence. The key architectural difference from traditional packaging is that the package is built up on the die itself as the starting material, rather than the die being mounted onto a pre-fabricated substrate.
| Stage | Function | Key Consideration |
|---|---|---|
| Die Placement on Carrier | Known-good dies placed face-down at target positions on a temporary carrier wafer with adhesive film | Placement accuracy determines downstream RDL alignment; typically ±5–10 µm target |
| Mold Reconstitution | Epoxy molding compound (EMC) compression-molded around dies to form a reconstituted wafer; carrier removed | Warpage management; EMC cure shrinkage distorts die positions; critical for RDL yield |
| RDL Build-Up | One or more redistribution layers patterned over the reconstituted wafer with fine-line copper traces and vias | RDL line/space at 2–10 µm; lithography tools adapted for reconstituted-wafer topography |
| Bump / Ball Attach | Solder balls or copper pillars attached to the RDL outer surface for board connection | Bump pitch tuned to package BGA footprint; typically 0.3–0.5 mm pitch for board assembly |
| Singulation & Test | Reconstituted wafer diced into individual fan-out packages; each package tested | Package thickness often under 0.5 mm; handling and test fixture design adapted for thin form factor |
Warpage is the central process-control challenge across the InFO flow. The reconstituted wafer is a silicon-and-EMC composite — dies (silicon CTE) embedded in molding compound (much higher CTE) — that bows and warps during thermal steps. Each RDL layer adds stress. Warpage management determines whether the reconstituted wafer remains flat enough for subsequent lithography alignment and for singulated packages to sit flat on a board at assembly. TSMC's InFO yield lead over OSAT fan-out has historically rested on proprietary warpage control.
InFO Variants
InFO is a family of variants rather than a single product. TSMC has expanded the InFO portfolio over multiple generations to serve different form factors and integration patterns. Each variant uses the fan-out core technology with structural modifications for its target application.
| Variant | Structure | Primary Use |
|---|---|---|
| InFO-PoP (Package-on-Package) | Fan-out bottom package with logic die; memory package stacked on top via through-InFO vias (TIV) | Mobile SoCs with integrated LPDDR memory; the original Apple iPhone InFO variant |
| InFO-oS (on-Substrate) | Fan-out module mounted on an organic substrate for board-level connection; enables higher pin counts | High-performance mobile and Mac SoCs (Apple M-series); SoCs with substantial pin count or memory integration |
| InFO-MS (Multi-Stack) | Multi-die fan-out with side-by-side dies in a single reconstituted wafer | System-in-package mobile and consumer products with heterogeneous dies (logic + specialty silicon) |
| InFO-SoW (System-on-Wafer) | Wafer-scale fan-out integration; the full reconstituted wafer (or a large portion) is the final module | Specialty high-integration applications; Cerebras-style wafer-scale silicon; emerging use in AI training hardware |
| InFO-LI (Local Interconnect) | Fan-out with embedded local silicon interconnect for die-to-die routing at higher density than RDL alone | Multi-die integration at mid-to-high bandwidth; serves customers between classic InFO and CoWoS tiers |
The InFO-PoP variant is the heritage implementation — Apple's adoption of InFO-PoP in the iPhone 7's A10 Fusion SoC (2016) was the volume inflection point that established fan-out as a mainstream packaging technology. Every subsequent Apple A-series generation has refined the InFO implementation. InFO-oS emerged alongside the transition to M-series Mac silicon, where the higher pin count and thermal requirements of a Mac SoC exceeded what InFO-PoP could deliver. InFO-SoW addresses wafer-scale integration and sits at the specialty end of the portfolio.
InFO vs. CoWoS
InFO and CoWoS are TSMC's two flagship advanced packaging architectures and they serve non-overlapping markets. Understanding the split is useful for understanding where each fits in the broader landscape.
| Dimension | InFO | CoWoS |
|---|---|---|
| Carrier | Reconstituted wafer (EMC) with RDL routing; no silicon interposer | Silicon interposer (CoWoS-S), RDL interposer (CoWoS-R), or embedded bridge (CoWoS-L) |
| Form Factor | Very thin profile (sub-0.5 mm typical); mobile-optimized | Thick multi-layer assembly with large substrate footprint; datacenter-optimized |
| Bandwidth Tier | Moderate; RDL routing limits pitch and frequency | Extreme; silicon interposer enables direct integration with HBM at thousands of signals |
| Target Applications | Mobile SoCs, Mac SoCs, consumer electronics, wearables, SiP | AI accelerators, HPC, high-bandwidth networking ASICs, hyperscaler custom silicon |
| Cost Tier | Medium; competitive with organic FCBGA at equivalent pin count | Very high; silicon interposer fabrication dominates cost |
The two architectures do not compete for capacity. InFO production runs at dedicated fan-out facilities; CoWoS runs at the silicon-interposer advanced packaging facilities. Capacity expansion for each is driven by its own customer demand trajectory.
Customer Applications
| Customer | Products on InFO | Variant |
|---|---|---|
| Apple | A10 Fusion through A-series current generation; M1, M2, M3, M4, subsequent M-series | InFO-PoP (A-series iPhone); InFO-oS (M-series Mac) |
| MediaTek | Dimensity flagship smartphone SoCs | InFO-PoP and InFO variants |
| Qualcomm | Select Snapdragon platforms | InFO variants for mobile SoC packaging |
| Tensor mobile SoCs and select server silicon | InFO-oS and related variants | |
| Automotive and specialty fabless | ADAS SoCs, automotive infotainment, specialty consumer silicon | Various InFO variants by product requirement |
Apple is the anchor customer and has been since the A10 Fusion introduction. Apple's volume sets the baseline for InFO capacity planning at TSMC, and every subsequent Apple SoC generation has refined the InFO implementation alongside process node transitions (InFO has evolved from 16 nm-era A10 through the current leading-edge Apple silicon generation). MediaTek is the second-largest InFO volume customer and has used InFO variants across its Dimensity flagship line. Qualcomm has used InFO in select flagship Snapdragon products, complementing its broader use of organic flip-chip packaging. Google's Tensor SoCs and specialty products use InFO for the mobile-tier integration they require.
Supply Chain & Equipment
InFO production depends on a supply chain that overlaps partially with CoWoS and partially with broader fan-out packaging.
| Input | Source | Concentration |
|---|---|---|
| Epoxy molding compound (EMC) | Sumitomo Bakelite, Nagase ChemteX, Resonac (Hitachi Chemical), specialty Japanese EMC suppliers | Japan-centered specialty chemicals; specialized fan-out EMC grades |
| RDL photoresist and dielectrics | JSR, Tokyo Ohka Kogyo, Shin-Etsu, specialty polymer suppliers | Japan-centered; overlaps with front-end photoresist supply base |
| RDL lithography and processing equipment | ASML, Canon, Nikon (exposure); Applied Materials, Lam Research, TEL (deposition, etch, CMP) | Same WFE vendor set as front-end wafer processing, adapted for reconstituted-wafer flow |
| Compression molding equipment | Towa, Apic Yamada, Boschman | Specialty compression-molding press supply |
| Organic substrate (InFO-oS only) | Unimicron, Ibiden, Nan Ya PCB, Shinko, Samsung Electro-Mechanics | Overlaps with CoWoS and general FCBGA substrate supply; see Substrates & Interposers |
A distinctive feature of fan-out packaging is the equipment overlap with front-end wafer processing. Because RDL formation uses lithography, deposition, etch, and CMP steps analogous to front-end interconnect, InFO production leverages the broader WFE equipment ecosystem rather than a dedicated back-end tool set. This is one of the reasons TSMC has been the leader in fan-out — the fab-adjacent process discipline translates naturally to the fan-out flow.
Capacity & Geography
InFO production runs primarily at TSMC advanced packaging facilities in Taiwan. Capacity is expanded alongside TSMC's overall advanced packaging buildout, with InFO expansion driven primarily by Apple's SoC roadmap plus the growing customer base at MediaTek, Qualcomm, Google, and specialty fabless. InFO Arizona capacity is part of the TSMC Arizona advanced packaging roadmap as customer programs require U.S. packaging.
The relationship between TSMC captive InFO and OSAT FO-WLP is complementary rather than directly competitive. TSMC's InFO serves the foundry-integrated tier (process co-optimization with the customer's logic die); OSAT FO-WLP serves a broader cost-sensitive mobile and consumer base. As FO-WLP capacity expands at OSATs and as panel-level fan-out (FOPLP) ramps, some mid-tier volume that historically went to InFO may migrate to OSATs. TSMC's InFO roadmap focus continues to be the high-performance tier and the variant family (InFO-oS, InFO-LI, InFO-SoW) that extends beyond the FO-WLP capability envelope.
Market Outlook
InFO demand tracks Apple's SoC volume plus the growing mobile and consumer fabless customer base. The technology is mature and has been in volume production across multiple generations. The active frontiers are: InFO-SoW for wafer-scale AI applications (growing but niche); InFO-LI for mid-bandwidth multi-die integration (growing as a CoWoS-R/L alternative at the lower-bandwidth end); InFO-oS capacity to support M-series and equivalent high-performance mobile/consumer silicon. Panel-level fan-out (FOPLP) adoption across the industry is the medium-term competitive pressure on wafer-level fan-out economics.
InFO will remain central to the mobile and consumer advanced packaging tier through the end of this decade. CoWoS and 3D hybrid bonding will continue to dominate AI/HPC packaging; InFO and OSAT FO-WLP will dominate mobile and consumer. The bifurcation between foundry-captive advanced packaging and OSAT fan-out is the durable structure.
Related Coverage
Parent: Advanced Packaging
Sibling fan-out architecture: FO-WLP (OSAT fan-out)
Contrasting TSMC architecture: CoWoS (2.5D silicon interposer for AI/HPC)
Peer advanced packaging architectures: Foveros · EMIB · I-Cube · SiP
Foundation layers: Substrates & Interposers (InFO-oS substrate) · Encapsulation (EMC for reconstituted wafer)
Cross-architecture reference: Comparison Matrix
Cross-pillar dependencies: Mobile SoCs (InFO consumer base) · Bottleneck Atlas