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Semiconductor Mfg Process Flow



A leading-edge logic chip passes through 500 to 1,000 process steps and roughly 90 mask layers over a three- to four-month cycle. Most of those steps are not unique. They are the same six-step loop — clean, deposit, pattern, etch, clean, measure — run 80 to 120 times on the same wafer. Fab cost, fab capex, and fab concentration all compound out of that inner loop: each iteration passes through tools made by fewer than twenty companies worldwide, installed in lines that now cost $15–20B at 2nm. This page maps the flow across its four segments and names the loop at its center.

Front-End Fab loops 80–120× Wafer Test sort / probe Assembly & Packaging dice, bond, encapsulate Module Integration chiplets, tiles, boards One wafer passes through the front-end loop up to ~120 times before moving downstream. Subsequent segments run once per die or module.

The Four Process Flow Segments

Semiconductor manufacturing is not one process. It is four sequential segments with very different iteration profiles, vendor concentrations, and capital structures. The front-end loop absorbs the majority of fab capex and tool diversity. Test, assembly, and module integration run once per unit but carry their own concentration stories — OSAT oligopoly in the back-end, advanced-packaging chokepoints (CoWoS, SoIC) in module integration.

SegmentWhat HappensIterationPrimary Concentration
Front-End Fabrication Transistors and interconnect are built layer by layer on the wafer80–120× per wafer (the layer-build loop)WFE oligopoly: ASML, AMAT, Lam, TEL, KLA control >70% of tool spend
Wafer Test Probe stations test each die on the wafer electrically; defective dies are inkedOnce per wafer passATE duopoly: Teradyne and Advantest
Back-End Assembly & Packaging Wafers are diced; dies are bonded, wired, and encapsulated in packagesOnce per dieOSAT top-tier: ASE, Amkor, JCET, SPIL, PTI
Module Integration Packaged dies combined into chiplets, tiles, superchips, boards, or wafer-scale modulesOnce per moduleAdvanced packaging bottleneck: TSMC CoWoS, Intel EMIB/Foveros, Samsung SAINT

The Semiconductor Layer-Build Loop

The single most important fact about front-end fabrication is that it is a loop, not a sequence. Each patterned layer of a chip — every transistor level, every metal interconnect level, every via — is built by running the wafer through the same six-step core cycle. A modern chip has 80 to 120 of these layers. The wafer passes through the loop once per layer, and in the process visits roughly 90 photomasks and executes 500–1,000 discrete steps before it reaches wafer test.

Repeat 80–120× per wafer 1. Clean prep surface 2. Deposit lay down film 3. Litho pattern film 4. Etch remove material 5. Clean strip resist 6. Metrology inspect / measure

Two steps in the loop — deposition and etch — come in many variants depending on the layer being built. Gate oxide deposition uses different chemistry than copper interconnect deposition; polysilicon etch uses different plasma than low-k dielectric etch. Ion implantation (doping) and oxidation sit outside the core loop and are invoked conditionally for specific layers, typically during transistor formation and well isolation. CMP (chemical mechanical planarization) is effectively a seventh step, folded into most loop passes to re-flatten the wafer before the next cycle can be patterned accurately.

Layer Count by Chip Type

Chip TypeLayer CountApprox. Mask LayersNotes
90nm CMOS logic35–50~30Legacy / analog / MCU baseline
7nm FinFET logic60–80~70First widespread EUV usage
3nm GAA logic80–120~90Gate-all-around; heavy EUV, selective multi-patterning
DRAM (planar)40–70~40Capacitor-formation dominant
3D NAND flash64–232+ (vertical stack)~60Vertical integration — high-aspect-ratio etch is the bottleneck

Front-End Step Inventory

Front-end steps group into three roles: surface preparation, layer construction, and electrical modification. The table below inventories them by role and links out to the tool category that performs each step.

StepRoleIterationTool Category
Wafer cleaningSurface prepEvery loop passWet benches / single-wafer cleaners
OxidationGrow insulating oxideSelective (gate / isolation layers)Thermal furnaces
Deposition (CVD, PVD, ALD, epitaxy)Add filmEvery loop passDeposition
Photoresist coatPrep for patterningEvery litho passCoater-developer tracks
Photolithography (exposure)Pattern transfer~90 mask layersLithography
DevelopReveal patternEvery litho passCoater-developer tracks
Etch (dry / wet)Remove unprotected materialEvery loop passEtch
Ion implantationDope siliconSelective (transistor regions)Implanters (AMAT, Axcelis)
CMPPlanarize surfaceMost loop passesCMP
MetallizationBuild interconnectMulti-level (BEOL stack)Deposition + electroplating
Metrology & inspectionVerify each layerEvery loop passMetrology & Inspection

Back-End & Module Integration Step Inventory

After the wafer leaves front-end fabrication and wafer test, it enters a shorter but more physically diverse set of steps. Back-end assembly converts the wafer into individual packaged chips. Module integration combines those packaged chips — or bare dies — into the multi-die, multi-substrate constructions that dominate modern AI and high-performance compute: chiplets, interposers, tiles, and wafer-scale modules.

StepRoleIterationTool / Facility
Wafer thinning / backgrindReduce wafer to target thicknessOnce per waferBackgrind tools (Disco, Accretech)
DicingSeparate wafer into diesOnce per waferDicing saws / laser / plasma
Die attachBond die to substrate or leadframeOnce per dieDie bonders (ASMPT, BESI, K&S)
Wire bonding / flip-chip bumpElectrical connection to packageOnce per dieWire bonders / bumping lines
Encapsulation / moldingProtect die and leadsOnce per packageMolding presses
Final test & burn-inValidate packaged partOnce per packageATE (Teradyne, Advantest)
Interposer / RDL buildCreate multi-die routing layerPer moduleAdvanced packaging lines (CoWoS, EMIB)
Multi-die bonding (2.5D / 3D)Stack or tile multiple diesPer moduleHybrid bonders (BESI/AMAT, TEL)
Module-level testValidate assembled moduleOnce per moduleSystem-level test platforms

Wafer Logistics Layer

Inside the fab, the wafer does not travel a fixed path. It moves between hundreds of single-purpose tools — often from different vendors — coordinated by a digital orchestration layer. This is why a fab is structurally unlike an automotive assembly line: there is no conveyor, no fixed sequence, and no guaranteed tool-to-tool adjacency. A wafer may visit the same etch module a dozen times across its manufacturing cycle, each time with a different recipe.

SystemRoleFunction
FOUP (Front-Opening Unified Pod)Wafer carrierHolds 25 wafers; isolates them from cleanroom air
EFEM (Equipment Front-End Module)Tool-side load portRobotic wafer transfer between FOUP and process chamber
AMHS (Automated Material Handling System)Fab-wide transportOverhead rail or floor vehicles move FOUPs tool-to-tool
MES (Manufacturing Execution System)Digital controlSchedules every wafer, tracks recipe history, routes by queue depth

Cost & Time Compounding

Because the layer-build loop repeats dozens of times, each iteration's cost is multiplied by the number of layers. Mask count, cycle time, and capex per fab line scale together as nodes advance. Beyond ~7nm, multi-patterning and high-NA EUV push mask count and step count nonlinearly relative to geometric shrink.

NodeMask LayersLine CapexCycle Time
14nm / 10nm~55$2–3B~10 weeks
7nm~70$4–6B~12 weeks
5nm~80$6–8B~13 weeks
3nm (GAA)~90$10–12B~14 weeks
2nm~95+$15–20B~16 weeks
sub-2nm100+$20B+16+ weeks

Cross-Pillar Context

Manufacturing flow is one of four axes that together describe how semiconductors are built. The other three treat the same activity from different structural lenses:

AxisLensHub
EquipmentThe tools that execute each stepFab Equipment
FacilitiesThe fabs and OSATs that house the toolsFab Facilities
ConsumablesThe materials the tools apply or removeProcess Consumables
Materials upstreamRaw substrates, gases, IP blocks feeding the flowMaterials & IP

Related Coverage

Upstream: Materials & IP · Process Consumables

Downstream: Chip Types · Sectors

Supporting: Fab Equipment · Fab Facilities · Fab Operations