Semiconductor Mfg Steps
Semiconductor devices are built layer by layer through hundreds of precise steps. Each “layer” refers to a distinct patterned structure added through deposition, etch, and lithography steps. Some layers are metal interconnects; others are transistors, vias, dielectrics, or implants. Some steps are performed once at the beginning of wafer production, while others are repeated dozens or even hundreds of times during front-end wafer fabrication for each layer of the chip.
Depending on the layer's purpose (e.g., polysilicon gate vs metal interconnect), the specific chemistries, equipment, and parameters will change — but the steps repeat in sequence, over and over again. This master flow outlines the order of operations and highlights which processes are iterative.
Each layer is built up using a subset of the same core steps, usually:
- Clean
- Deposition (of a film)
- Lithography (to define pattern)
- Etch (to remove material)
- Clean
- Metrology & inspection
Typical Layer Count by Chip Type
A high-end chip can involve 80–120+ layers, each requiring its own photolitho + etch cycle. The fab is like a giant circuit city, where wafers loop through complex toolsets hundreds of times before completion.
| Chip Type | Estimated Layer Count |
|---|---|
| 90nm CMOS Logic | ~35–50 layers |
| 7nm FinFET Logic | ~60–80 layers |
| 3nm GAA Logic | ~80–120 layers |
| DRAM (planar) | ~40–70 layers |
| 3D NAND Flash | 64–232+ layers (vertical stack) |
Step-by-Step Flow
Wafers move from tool to tool inside FOUPs and travel in loops throughout the fab.
| Order | Step | Type | Iteration | Purpose |
|---|---|---|---|---|
| 3 | Oxidation | Front-End | Multiple (layer-specific) | Grow insulating oxides for gates/isolation |
| 4 | Cleaning | Front-End | Repeated (every cycle) | Remove residues before each process |
| 5 | Deposition | Front-End | Repeated | Lay down thin films of materials |
| 6 | Photoresist Coating | Front-End | Repeated | Apply resist layer for lithography |
| 7 | Photolithography (Expose & Develop) | Front-End | Repeated | Transfer patterns onto wafer |
| 8 | Etching | Front-End | Repeated | Remove unprotected material |
| 9 | Doping (Ion Implantation) | Front-End | Multiple (select layers) | Introduce dopants to control conductivity |
| 10 | Planarization (CMP) | Front-End | Repeated (layer by layer) | Flatten wafer surface before next cycle |
| 11 | Metallization | Front-End | Multiple (multi-level interconnect) | Create interconnect wiring layers |
| 12 | Die Preparation | Back-End | One-time | Dice wafers into individual dies |
| 13 | Packaging | Back-End | One-time | Encapsulate die, provide I/O and thermal paths |
| 14 | Testing | Back-End | One-time (final + burn-in) | Validate performance and reliability |
Iteration Notes
- One-time steps: Crystal growing, wafer slicing, die prep, packaging, test.
- Repeated steps: Cleaning, deposition, lithography, etching, planarization. Each wafer can undergo these cycles hundreds of times.
- Conditional steps: Oxidation and doping are applied selectively depending on device architecture.
How Wafers Move Through the Fab
| System | Function |
|---|---|
| FOUP (Front-Opening Unified Pod) | Holds 25 wafers; protects them from contamination between tools |
| EFEM (Equipment Front-End Module) | Loads wafers into tools; handles robotic transfer and alignment |
| AMHS (Automated Material Handling System) | Automated tracks or overhead robots move FOUPs to the next station |
| MES (Manufacturing Execution System) | Digital control system tracks each wafer, tool queue, and recipe |
Toolset Groupings
Each of the following toolsets exists as standalone systems, often from different vendors:
- Coater-Developer tracks (Tokyo Electron)
- Steppers/Scanners (ASML)
- Plasma Etchers (Lam, TEL)
- Oxidation or Implant tools
- Metrology stations (KLA)
- Wet benches / scrubbers
They are networked together via the fab’s automation system (AMHS + MES), not physically connected like an assembly line.
Fab Workflow Summary
The wafer does not follow a fixed linear path. Instead, it loops through a complex web of single-purpose tools— each one performing a specialized step such as etching, measuring, or coating. The flow is orchestrated by a digital manufacturing system that tracks each wafer’s progress and ensures every layer is completed with atomic precision.
FAQ
Q: Do all layers require lithography?
A: Most layers do, especially those with patterning needs. Some deposition or fill layers may be blanket films without litho steps.
Q: Are all wafers processed the same way?
A: No. Flow varies by chip type, design rules, and node. Advanced logic requires many more steps than legacy or analog chips.
Q: Can tools process multiple wafers at once?
A: Some tools (e.g., furnaces, wet benches) handle batches; others (e.g., litho, etch) typically process wafers one at a time.
Step Definitions
Design and Mask Making: Before actual manufacturing begins, semiconductor devices are designed using sophisticated software. The design is then transferred onto masks, which are templates used in later stages for patterning the semiconductor material.
Crystal Growing: This is the first step where pure silicon is grown into monocrystalline ingots using methods like the Czochralski process. Silicon is the most commonly used base material due to its semiconductor properties.
Wafer Preparation: The silicon ingots are sliced into thin wafers using a precision saw. These wafers are then polished to create a flat, smooth surface.
Cleaning: Wafers are meticulously cleaned using a combination of chemical and physical methods to remove any contaminants. This step is repeated multiple times throughout the manufacturing process to maintain a contaminant-free environment.
Oxidation: Silicon wafers are exposed to oxygen or steam at high temperatures to grow a layer of silicon dioxide on their surface. This layer acts as an insulator or as a mask against dopants.
Deposition: Various materials are deposited onto the wafer using techniques like Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD). Deposition is used to create various layers needed for the ICs and is a step that's repeated for each layer.
Photoresist Application: A light-sensitive material, known as photoresist, is applied to the wafer's surface. The photoresist is used to transfer a pattern onto the wafer.
Photolithography: This process involves exposing the photoresist-covered wafer to ultraviolet light through a photomask, which transfers the circuit pattern. Photolithography is repeated for each layer of the IC.
Development: After exposure, the wafer is developed, which removes the exposed or unexposed photoresist (depending on the type of photoresist used), revealing the underlying material in the pattern of the photomask.
Etching: The exposed areas of the wafer surface are removed through etching, using either wet or dry etching methods. Etching is used to create the actual circuit patterns on the wafer.
Doping: Impurities are introduced into the silicon wafer to change its electrical properties. Doping methods include ion implantation and diffusion. This step is repeated for different regions of the IC.
Planarization: Particularly Chemical Mechanical Planarization (CMP) is used to flatten the wafer surface. This is essential for ensuring a flat surface for subsequent photolithography steps.
Metallization: Metal layers are added to the wafer to create electrical connections. This usually involves depositing layers of metals like aluminum or copper.
Wafer Testing: The wafers are tested for electrical functionality. Defective parts are marked and will be discarded after slicing.
Die Preparation: This involves applying a protective layer and additional patterning steps specific to the individual ICs.
Die Slicing: The processed wafer is sliced into individual dies or chips.
IC Packaging: Each die is packaged into a protective casing that provides connections to the outside world.
IC Testing: The final step involves testing the individual ICs for functionality and performance.
