SemiconductorX > Fab & Assembly > Manufacturing Flow
Semiconductor Mfg Process Flow
A leading-edge logic chip passes through 500 to 1,000 process steps and roughly 90 mask layers over a three- to four-month cycle. Most of those steps are not unique. They are the same six-step loop — clean, deposit, pattern, etch, clean, measure — run 80 to 120 times on the same wafer. Fab cost, fab capex, and fab concentration all compound out of that inner loop: each iteration passes through tools made by fewer than twenty companies worldwide, installed in lines that now cost $15–20B at 2nm. This page maps the flow across its four segments and names the loop at its center.
The Four Process Flow Segments
Semiconductor manufacturing is not one process. It is four sequential segments with very different iteration profiles, vendor concentrations, and capital structures. The front-end loop absorbs the majority of fab capex and tool diversity. Test, assembly, and module integration run once per unit but carry their own concentration stories — OSAT oligopoly in the back-end, advanced-packaging chokepoints (CoWoS, SoIC) in module integration.
| Segment | What Happens | Iteration | Primary Concentration |
|---|---|---|---|
| Front-End Fabrication | Transistors and interconnect are built layer by layer on the wafer | 80–120× per wafer (the layer-build loop) | WFE oligopoly: ASML, AMAT, Lam, TEL, KLA control >70% of tool spend |
| Wafer Test | Probe stations test each die on the wafer electrically; defective dies are inked | Once per wafer pass | ATE duopoly: Teradyne and Advantest |
| Back-End Assembly & Packaging | Wafers are diced; dies are bonded, wired, and encapsulated in packages | Once per die | OSAT top-tier: ASE, Amkor, JCET, SPIL, PTI |
| Module Integration | Packaged dies combined into chiplets, tiles, superchips, boards, or wafer-scale modules | Once per module | Advanced packaging bottleneck: TSMC CoWoS, Intel EMIB/Foveros, Samsung SAINT |
The Semiconductor Layer-Build Loop
The single most important fact about front-end fabrication is that it is a loop, not a sequence. Each patterned layer of a chip — every transistor level, every metal interconnect level, every via — is built by running the wafer through the same six-step core cycle. A modern chip has 80 to 120 of these layers. The wafer passes through the loop once per layer, and in the process visits roughly 90 photomasks and executes 500–1,000 discrete steps before it reaches wafer test.
Two steps in the loop — deposition and etch — come in many variants depending on the layer being built. Gate oxide deposition uses different chemistry than copper interconnect deposition; polysilicon etch uses different plasma than low-k dielectric etch. Ion implantation (doping) and oxidation sit outside the core loop and are invoked conditionally for specific layers, typically during transistor formation and well isolation. CMP (chemical mechanical planarization) is effectively a seventh step, folded into most loop passes to re-flatten the wafer before the next cycle can be patterned accurately.
Layer Count by Chip Type
| Chip Type | Layer Count | Approx. Mask Layers | Notes |
|---|---|---|---|
| 90nm CMOS logic | 35–50 | ~30 | Legacy / analog / MCU baseline |
| 7nm FinFET logic | 60–80 | ~70 | First widespread EUV usage |
| 3nm GAA logic | 80–120 | ~90 | Gate-all-around; heavy EUV, selective multi-patterning |
| DRAM (planar) | 40–70 | ~40 | Capacitor-formation dominant |
| 3D NAND flash | 64–232+ (vertical stack) | ~60 | Vertical integration — high-aspect-ratio etch is the bottleneck |
Front-End Step Inventory
Front-end steps group into three roles: surface preparation, layer construction, and electrical modification. The table below inventories them by role and links out to the tool category that performs each step.
| Step | Role | Iteration | Tool Category |
|---|---|---|---|
| Wafer cleaning | Surface prep | Every loop pass | Wet benches / single-wafer cleaners |
| Oxidation | Grow insulating oxide | Selective (gate / isolation layers) | Thermal furnaces |
| Deposition (CVD, PVD, ALD, epitaxy) | Add film | Every loop pass | Deposition |
| Photoresist coat | Prep for patterning | Every litho pass | Coater-developer tracks |
| Photolithography (exposure) | Pattern transfer | ~90 mask layers | Lithography |
| Develop | Reveal pattern | Every litho pass | Coater-developer tracks |
| Etch (dry / wet) | Remove unprotected material | Every loop pass | Etch |
| Ion implantation | Dope silicon | Selective (transistor regions) | Implanters (AMAT, Axcelis) |
| CMP | Planarize surface | Most loop passes | CMP |
| Metallization | Build interconnect | Multi-level (BEOL stack) | Deposition + electroplating |
| Metrology & inspection | Verify each layer | Every loop pass | Metrology & Inspection |
Back-End & Module Integration Step Inventory
After the wafer leaves front-end fabrication and wafer test, it enters a shorter but more physically diverse set of steps. Back-end assembly converts the wafer into individual packaged chips. Module integration combines those packaged chips — or bare dies — into the multi-die, multi-substrate constructions that dominate modern AI and high-performance compute: chiplets, interposers, tiles, and wafer-scale modules.
| Step | Role | Iteration | Tool / Facility |
|---|---|---|---|
| Wafer thinning / backgrind | Reduce wafer to target thickness | Once per wafer | Backgrind tools (Disco, Accretech) |
| Dicing | Separate wafer into dies | Once per wafer | Dicing saws / laser / plasma |
| Die attach | Bond die to substrate or leadframe | Once per die | Die bonders (ASMPT, BESI, K&S) |
| Wire bonding / flip-chip bump | Electrical connection to package | Once per die | Wire bonders / bumping lines |
| Encapsulation / molding | Protect die and leads | Once per package | Molding presses |
| Final test & burn-in | Validate packaged part | Once per package | ATE (Teradyne, Advantest) |
| Interposer / RDL build | Create multi-die routing layer | Per module | Advanced packaging lines (CoWoS, EMIB) |
| Multi-die bonding (2.5D / 3D) | Stack or tile multiple dies | Per module | Hybrid bonders (BESI/AMAT, TEL) |
| Module-level test | Validate assembled module | Once per module | System-level test platforms |
Wafer Logistics Layer
Inside the fab, the wafer does not travel a fixed path. It moves between hundreds of single-purpose tools — often from different vendors — coordinated by a digital orchestration layer. This is why a fab is structurally unlike an automotive assembly line: there is no conveyor, no fixed sequence, and no guaranteed tool-to-tool adjacency. A wafer may visit the same etch module a dozen times across its manufacturing cycle, each time with a different recipe.
| System | Role | Function |
|---|---|---|
| FOUP (Front-Opening Unified Pod) | Wafer carrier | Holds 25 wafers; isolates them from cleanroom air |
| EFEM (Equipment Front-End Module) | Tool-side load port | Robotic wafer transfer between FOUP and process chamber |
| AMHS (Automated Material Handling System) | Fab-wide transport | Overhead rail or floor vehicles move FOUPs tool-to-tool |
| MES (Manufacturing Execution System) | Digital control | Schedules every wafer, tracks recipe history, routes by queue depth |
Cost & Time Compounding
Because the layer-build loop repeats dozens of times, each iteration's cost is multiplied by the number of layers. Mask count, cycle time, and capex per fab line scale together as nodes advance. Beyond ~7nm, multi-patterning and high-NA EUV push mask count and step count nonlinearly relative to geometric shrink.
| Node | Mask Layers | Line Capex | Cycle Time |
|---|---|---|---|
| 14nm / 10nm | ~55 | $2–3B | ~10 weeks |
| 7nm | ~70 | $4–6B | ~12 weeks |
| 5nm | ~80 | $6–8B | ~13 weeks |
| 3nm (GAA) | ~90 | $10–12B | ~14 weeks |
| 2nm | ~95+ | $15–20B | ~16 weeks |
| sub-2nm | 100+ | $20B+ | 16+ weeks |
Cross-Pillar Context
Manufacturing flow is one of four axes that together describe how semiconductors are built. The other three treat the same activity from different structural lenses:
| Axis | Lens | Hub |
|---|---|---|
| Equipment | The tools that execute each step | Fab Equipment |
| Facilities | The fabs and OSATs that house the tools | Fab Facilities |
| Consumables | The materials the tools apply or remove | Process Consumables |
| Materials upstream | Raw substrates, gases, IP blocks feeding the flow | Materials & IP |
Related Coverage
Upstream: Materials & IP · Process Consumables
Downstream: Chip Types · Sectors
Supporting: Fab Equipment · Fab Facilities · Fab Operations