3D IC Packaging

3D IC is the umbrella category for advanced packaging architectures that stack dies vertically — one die physically on top of another — rather than placing them side-by-side on an interposer (2.5D) or on a substrate (traditional packaging). The architectural advantages are structural: interconnect distances shrink from millimeters (2.5D interposer routing) to micrometers (vertical TSVs or hybrid bonds); signal latency drops accordingly; power delivery paths shorten; and the module footprint on the board shrinks because dies stack rather than spread. The challenges are equally structural: heat from lower dies must exit through upper dies before reaching a heat spreader; yield compounds with stack height; the vertical interconnects (TSVs, micro-bumps, hybrid bonds) require fabrication and process disciplines drawn from front-end rather than traditional back-end.

Four concrete 3D architectures are in production at scale today: TSMC SoIC (System on Integrated Chips, TSMC's hybrid-bonded die-on-die platform); Intel Foveros and its hybrid-bonded successor Foveros Direct (Intel's 3D stacking for client CPUs and beyond); Samsung SAINT (Samsung Foundry's 3D stacking platform); and HBM stacking (stacked DRAM with TSVs or hybrid bonding, which is itself a 3D packaging technology that has become the volume driver for 3D integration broadly). A fifth category — CMOS image sensors — has been using wafer-to-wafer 3D integration for over a decade and is the volume heritage that proved the technology. Full detail for each architecture lives on its own page; this hub page maps the 3D landscape and explains what's common across the family.

The die-to-die interconnect technology inside a 3D stack is either TSV + micro-bump (the older generation, still in volume production) or hybrid bonding (the newer Cu-Cu direct-bonding generation at sub-10 µm pitch). The transition from micro-bumps to hybrid bonding at the die-to-die interface is the active generational shift in 3D packaging. Full treatment of the interconnect technologies lives at Advanced Interconnects.

Why 3D Exists as a Distinct Category

3D is architecturally distinct from 2.5D, not just a "denser" version of it. The differences are geometric and consequential.

The two categories serve different architectural purposes rather than competing directly. 2.5D excels at integrating high-bandwidth memory (HBM) alongside compute logic at extreme bandwidth — the AI accelerator use case is canonical. 3D excels at stacking logic on logic (compute tile on I/O tile, cache on compute die, accelerator on processor) at shorter-than-2.5D interconnect distances. Many products combine both: CoWoS plus SoIC at TSMC, EMIB plus Foveros at Intel, I-Cube plus SAINT at Samsung. The two-axis integration pattern lets designers choose the right architecture for each die-to-die interface in a module.

The 3D Architecture Landscape

The table below maps the named 3D architectures across the three major foundries plus the specialty heritage applications. Each architecture gets full treatment on its own page or via the linked source; this table is the orientation map.

Note that 3D NAND is a different category from packaging 3D IC — 3D NAND refers to vertical cell integration inside a single die during front-end fabrication, not to die-on-die stacking at the packaging level. It shares the "3D" label but is fabricated monolithically rather than assembled from multiple dies. HBM stacks, by contrast, are a packaging 3D technology: each HBM stack is assembled from multiple discrete DRAM dies plus a logic base die at the packaging stage.

TSMC SoIC in Focus

TSMC SoIC (System on Integrated Chips) is the TSMC 3D stacking platform and the production-anchor 3D hybrid-bonding architecture in the industry today. SoIC uses hybrid bonding at the die-to-die interface (rather than micro-bumps) from the first generation, which distinguishes it from original-generation Foveros and SAINT. The hybrid bonding pitch runs at sub-10 µm with the clear roadmap toward tighter pitches; the interconnect density is an order of magnitude finer than comparable micro-bump-based 3D platforms.

The architectural pattern of SoIC is die-on-die stacking without an intermediate interposer. Where Foveros uses an active base die with TSVs as a de facto active interposer beneath the upper tiles, SoIC bonds dies directly to each other — the top die's active surface bonds directly to the bottom die's active surface, with copper pads aligning metallically and dielectric surfaces bonding between them. The result is the shortest possible die-to-die interconnect path in any production 3D architecture.

The anchor production application for SoIC is AMD 3D V-Cache. AMD's Ryzen X3D desktop CPUs and EPYC X server CPUs use SoIC to bond an SRAM cache die on top of the CPU compute die, expanding L3 cache capacity by orders of magnitude without extending die area. The V-Cache approach has demonstrated SoIC's commercial viability for die-on-die logic stacking and has established AMD as the anchor SoIC customer. Additional SoIC customers are ramping as TSMC expands capacity and as chiplet architectures spread across the AI accelerator and HPC customer base.

SoIC production runs captive at TSMC advanced packaging facilities in Taiwan, with capacity expansion alongside the broader CoWoS-plus-SoIC advanced packaging buildout. Hybrid bonding equipment for SoIC comes from the BESI-Applied Materials partnership and Tokyo Electron — the same concentrated equipment base that gates Foveros Direct and HBM4 hybrid bonding.

The TSV-and-Bonding Shared Process Elements

Every 3D architecture shares a common set of process elements regardless of which operator runs it. These shared elements define what 3D packaging fabrication requires.

The convergence toward hybrid bonding as the die-to-die interconnect technology across all 3D architectures is the central trajectory in 3D packaging. SoIC ships hybrid bonding from inception. Foveros Direct replaces Foveros micro-bumps with hybrid bonding. HBM4 introduces hybrid bonding at the HBM die-to-die interface. SAINT's roadmap targets hybrid bonding adoption. This convergence concentrates pressure on the hybrid bonding equipment supply — BESI-Applied Materials and Tokyo Electron — which is one of the tightest bottlenecks in next-generation advanced packaging capacity, on par with CoWoS capacity in strategic significance.

Thermal Management

Thermal management is the discipline that limits 3D adoption more than any other single factor. In a stacked assembly, heat generated in the bottom die must exit through the upper dies before reaching the heat spreader or cold plate. Upper dies act as thermal resistance in series with the heat spreader. Compute-logic dies at high power density (AI accelerators, high-performance CPUs) can generate hundreds of watts per die; stacking them amplifies the challenge geometrically.

Design responses vary by architecture. SoIC places cache dies (lower power density) on top of compute dies to minimize heat-path impact. Foveros places compute tiles on top of a relatively lower-power base die so that heat exits directly from the compute tiles to the lid. HBM stacks use DRAM dies (lower power) that can be stacked with less thermal penalty than stacking multiple compute dies. For the highest-power programs — AI accelerators stacking multiple compute or accelerator tiles — specialty thermal interfaces (liquid metal TIMs, diamond-filled TIMs), integrated vapor chambers, and emerging direct-die liquid cooling are all under development.

Microfluidic cooling — channels etched into one or more silicon layers of the stack, carrying liquid coolant — is a research direction that could unlock significantly higher stack power density at the cost of substantial fabrication complexity. Production adoption remains limited; the technique is watched as a potential enabler for the next generation of high-power 3D modules.

Yield & Known-Good Die

Yield compounds with stack count in 3D assemblies. If each die in a stack is tested at 99% yield individually, a 4-die stack yields 0.99⁴ ≈ 96% even assuming perfect assembly — and real assembly processes introduce additional yield loss from bonding defects, placement misalignment, and warpage. At higher stack counts (HBM stacks with 8, 12, or 16 DRAM dies plus a base die), the yield math becomes punishing if individual die yields aren't extremely high.

The discipline response is known-good die (KGD) testing. Before a die is committed to a 3D stack, it is tested to functional and parametric specifications at the wafer level (wafer sort) and often re-tested at the singulated die level (die sort). Only verified known-good dies are used in stacking. This adds a test step and adds cost — but it prevents the geometric yield collapse that would otherwise occur. KGD requirements are higher for 3D assemblies than for comparable 2.5D modules because 3D stack failures scrap more silicon per failure.

HBM production has the most mature KGD discipline in the industry — HBM vendors have been fabricating multi-die stacks at scale for over a decade and have built the infrastructure for testing DRAM dies to the tight specifications required for stack assembly. The logic-stacking 3D architectures (SoIC, Foveros, SAINT) have adapted KGD practices from the HBM experience and from CMOS image sensor wafer-to-wafer bonding.

Market Outlook

3D IC adoption is expanding across AI accelerators (chiplet stacking at SoIC and Foveros Direct), HPC processors (3D V-Cache and successors), server CPUs with HBM integration (EMIB and CoWoS-paired HBM), and mobile (DRAM-on-logic stacking in select mobile programs). The volume driver through this decade remains HBM — every AI accelerator ships with multiple HBM stacks and HBM volume scales directly with AI accelerator production. The high-performance logic stacking tier (SoIC, Foveros Direct, SAINT) is smaller in unit volume but high in per-unit value and capacity-constrained on hybrid bonding equipment.

The long-term trajectory is that 3D integration becomes a broader architectural default for high-performance silicon, with hybrid bonding as the universal die-to-die interconnect at the finest pitches. Thermal management and yield remain the limiting discipline frontiers. 2.5D packaging (CoWoS, I-Cube, EMIB) will continue to dominate where HBM integration and lateral bandwidth are the priorities; 3D will dominate where vertical density and interconnect length matter most. Most high-performance modules in the next generation will use both in combination.

Related Coverage

Parent: Advanced Packaging

Peer 2.5D architectures: CoWoS · EMIB · I-Cube

3D architecture pages: Foveros (incl. Foveros Direct) · SAINT

Foundation interconnect layer: Advanced Interconnects (TSVs, micro-bumps, hybrid bonding in depth)

Cross-architecture reference: Comparison Matrix

Cross-pillar dependencies: HBM (volume 3D technology) · AI Accelerators (SoIC and Foveros Direct consumers) · CMOS Image Sensors (W2W heritage) · Bottleneck Atlas (hybrid bonding equipment constraint)