GPUs

Graphics Processing Units are massively parallel processors with thousands of compute cores, high-bandwidth memory stacks, and specialized matrix engines for mixed-precision arithmetic. Originally designed for graphics rendering, GPUs became the default AI training accelerator because of their architectural match to the linear algebra operations that define neural network training — and because NVIDIA built a software ecosystem (CUDA, cuDNN, NCCL, TensorRT) over fifteen years that made GPUs the path of least resistance for AI researchers and engineers.

The AI training GPU market is the most supply-constrained product category in semiconductors. NVIDIA H100, H200, and B200 face a stacked bottleneck structure — TSMC N4/N3 wafer allocation for the GPU die, CoWoS advanced packaging capacity at TSMC to integrate the die with HBM stacks, and SK Hynix HBM3E supply for the memory — where all three constraints operate on different physical resources and different expansion timelines. Relieving one does not relieve the others. This structure has made GPU supply the gating constraint on AI infrastructure buildout globally since 2023.

GPU Families — Products & Process

Deployment & Supply Chain Risk

The Stacked Bottleneck

The NVIDIA H100/B200 supply chain is the defining bottleneck in AI infrastructure. Three independent constraints apply simultaneously to every GPU that ships:

TSMC N4/N3 wafer starts. The GPU compute die is fabricated at TSMC N4 (Hopper) or N4P (Blackwell). This wafer allocation competes with AMD EPYC, Apple M-series, Qualcomm, and every other fabless company at the same node. TSMC prioritizes its largest customers, and NVIDIA's datacenter GPU volumes make it a top-tier allocation priority — but the pool is still finite and shared.

CoWoS packaging at TSMC. After wafer fabrication, the GPU die must be integrated with HBM stacks on a silicon interposer using TSMC's CoWoS process. CoWoS capacity is physically separate from wafer fab capacity and was the binding shipment constraint on H100 supply during 2023–2024. TSMC has been expanding CoWoS aggressively, but the lead time means this remains a structural constraint through the Blackwell generation.

SK Hynix HBM3E supply. SK Hynix supplies the dominant share of HBM3E for B200. Samsung is qualifying as a second source. Micron is ramping as a third. The three-supplier qualification process is multi-year, and the B200's 8-stack × 24GB = 192GB HBM3E configuration per GPU consumes significantly more HBM wafer area per unit than the H100's 6-stack configuration.

CUDA Ecosystem Lock-In

NVIDIA's competitive moat is not the GPU die — it is the CUDA software ecosystem built over fifteen years. PyTorch, TensorFlow, and JAX are all CUDA-native. cuDNN, cuBLAS, NCCL, and TensorRT are NVIDIA-proprietary libraries with no fully drop-in equivalents. The majority of AI research code is written assuming CUDA availability. AMD's ROCm ecosystem has made significant progress and supports major frameworks, but the friction of porting CUDA kernels, the performance gap on custom kernel operations, and the smaller community of ROCm-experienced engineers creates a switching cost that is not primarily financial — it is time and engineering capacity. This software lock-in is a supply chain risk because it concentrates AI infrastructure demand on a single GPU architecture in a way that cannot be diversified simply by qualifying a second hardware supplier.

Export Controls & Supply Chain Bifurcation

US export controls on advanced AI GPUs — implemented in successive rounds from October 2022 through 2024 — have created a bifurcated GPU supply chain. NVIDIA H100, H200, and B200 are restricted for export to China and a broad set of countries without specific licenses. NVIDIA has developed compliant variants (H20, L20, L2) with reduced compute performance that meet export control thresholds — these are the only NVIDIA datacenter GPUs legally available in China. Huawei Ascend 910B and 910C have emerged as the primary domestic Chinese alternative, fabricated at SMIC on a 7nm-class process. The bifurcation creates two parallel GPU supply chains: the TSMC/NVIDIA/SK Hynix chain serving Western AI infrastructure, and the SMIC/Huawei chain serving Chinese AI infrastructure — with different process nodes, different software ecosystems, and different memory architectures.

Related Coverage

Compute & Logic Hub | CPUs | AI Accelerators | HBM Supply Chain | AI Inference & Edge Compute SoCs | CoWoS Advanced Packaging | Semiconductor Bottleneck Atlas | NVIDIA Spotlight

Cross-Network — ElectronsX Demand Side

Every AI model deployed in an EV, AV, or humanoid robot was trained on GPU clusters. The training infrastructure — H100/B200 clusters consuming megawatts of power — is the upstream demand signal for the datacenter power, cooling, and grid interconnection buildout covered across ElectronsX. Robotics sim-to-real pipelines generating synthetic training data for robot manipulation and navigation are an emerging GPU demand category tied directly to humanoid robot deployment scale.

EX: ADAS/AV Compute Architecture | EX: Humanoid Robots | EX: Supply Chain Convergence Map