SemiconductorX > Fab & Assembly > Back-End Assembly & Packaging > Advanced Packaging > EMIB
EMIB Packaginh
EMIB — Embedded Multi-Die Interconnect Bridge — is Intel's 2.5D advanced packaging technology and the cost-optimized alternative to full silicon-interposer 2.5D (CoWoS, I-Cube). Instead of placing all side-by-side dies on a large silicon interposer that covers the full module footprint, EMIB embeds small silicon bridges into an organic substrate exactly where high-density die-to-die routing is required. Over the rest of the module area, standard organic substrate routing handles power, ground, and lower-speed signals. Each bridge is a few tens of square millimeters of silicon — small enough to be fabricated cheaply, large enough to deliver thousands of fine-pitch connections where two dies meet.
EMIB has been in volume production at Intel for close to a decade. Stratix 10 FPGAs introduced EMIB commercially, using the technology to connect the FPGA fabric to high-speed transceiver dies and HBM memory. Agilex FPGAs continued the pattern with more aggressive multi-die integration. Sapphire Rapids Xeon server CPUs with HBM use EMIB to bridge between the compute tiles and the HBM stacks integrated on the same substrate. Ponte Vecchio combines EMIB with Foveros to integrate 40+ chiplets — EMIB bridges handle lateral connections between compute columns while Foveros handles vertical stacking within each column. EMIB runs captive at Intel advanced packaging facilities in the United States.
The closest structural peer is TSMC CoWoS-L, which uses the same bridge concept within the CoWoS architecture family. Where CoWoS-L is a relatively recent addition to TSMC's advanced packaging portfolio, EMIB has been Intel's volume 2.5D architecture for longer and has seen broader product deployment. Samsung's bridge-based advanced packaging is the parallel effort at Samsung Foundry. The three bridge-based 2.5D approaches — EMIB, CoWoS-L, and Samsung — now coexist as the cost-optimized alternative to full silicon interposer across the three major foundries.
The Bridge Concept
The EMIB structural insight is that high-density die-to-die routing is only needed in a small zone — the area directly between two adjacent dies that communicate at high bandwidth. The rest of the module area (under each die individually, and between widely separated dies) doesn't need interposer-class density; it needs power delivery, ground routing, and lower-speed I/O, all of which organic substrate routing handles well. Placing a small silicon bridge only under the high-density zone gets the benefit of silicon-interposer routing where it matters without paying the cost of silicon across the full module.
| Architecture Element | EMIB Approach | Full Interposer Approach (CoWoS-S) |
|---|---|---|
| High-density die-to-die routing | Small silicon bridge(s) embedded in organic substrate at inter-die boundaries | Full silicon interposer spanning all dies, with back-end-of-line copper routing across |
| Power delivery, ground, low-speed I/O | Organic substrate routing at standard FCBGA density | Through-silicon vias down to organic substrate below interposer |
| Silicon area consumed | Sum of bridge areas; typically tens to hundreds of mm² total | Full module footprint; hundreds to thousands of mm² |
| Cost driver | Bridge silicon cost plus substrate embedding process | Silicon interposer fabrication including TSV array across full area |
| Die-to-die bandwidth | High at each bridge; topology-flexible with multiple bridges | Highest; unified routing across full interposer area |
The tradeoff is real. Full silicon interposers deliver higher total die-to-die bandwidth because routing runs continuously across the full module area rather than only at bridge zones. For AI accelerators with very wide memory bandwidth requirements (a logic die connected to 8+ HBM stacks with thousands of signals to each), the full interposer remains the preferred architecture. For products with more localized high-bandwidth requirements — a compute die connected to one or two HBM stacks on one side, transceivers on another, other compute on a third — EMIB's bridge-per-interface approach delivers the required bandwidth at much lower cost and with greater topology flexibility.
Bridge Fabrication & Embedding
An EMIB bridge is a piece of silicon containing multiple layers of fine-pitch copper routing. Bridges are fabricated on silicon wafers at Intel using processes similar to back-end-of-line wafer processing: dielectric deposition, copper damascene routing, via formation. The wafer is then thinned and singulated into individual bridges, which are embedded into the organic substrate during substrate fabrication.
The embedding process is a substrate-fabricator specialty. The bridge is placed into a cavity in the core or intermediate layer of the organic substrate; subsequent substrate build-up layers laminate over the bridge, with build-up vias providing the electrical connection from the bridge's top surface to the substrate's outer surface where the dies will attach. The embedded bridge is invisible in the finished substrate — what the assembly line sees is a standard FCBGA substrate with high-density pad clusters in the zones where bridges sit underneath.
Bridge embedding equipment and process expertise sit at Intel captive capacity and at a narrow set of substrate fabricators qualified to embed bridges into advanced FCBGA substrates for Intel. The specialty know-how is one of the moats around EMIB production — even if the bridge concept is straightforward, the substrate-embedding integration has decades of Intel-specific development behind it.
Assembly Flow
| Step | Action | Yield Focus |
|---|---|---|
| Substrate Arrival | Substrate with bridge(s) pre-embedded arrives at Intel advanced packaging line from substrate fabricator | Substrate-level bridge connectivity verified at substrate supplier before shipment |
| Die Placement | Adjacent dies flip-chip placed onto substrate with pad alignment to both standard FCBGA pads and bridge pads | Placement accuracy must satisfy both coarse-pitch and fine-pitch bump zones simultaneously |
| Reflow & Underfill | Solder reflow forms all die-to-substrate connections including over-bridge fine-pitch; underfill fills beneath each die | Uniform joint formation across die area despite topography variation over embedded bridges |
| Encapsulation & Lid Attach | Module encapsulated and lidded for thermal path to heatsink; module-level test verifies full multi-die functionality | Thermal design across multi-die module; module-level test including KGD verification |
The assembly flow is familiar flip-chip assembly with additional alignment constraints at the bridge zones. Placement accuracy is the critical parameter — a die must land correctly on both its standard FCBGA pads (which might be at tens-of-µm pitch) and on the bridge pads underneath (which are at much finer pitch). Intel's advanced packaging lines are calibrated for this two-pitch alignment, and the thermocompression bonding (TCB) variant is used at the finest bridge pitches.
Representative Products
| Product | Type | EMIB Role |
|---|---|---|
| Intel Stratix 10 | FPGA (2016) | First commercial EMIB deployment; connects FPGA fabric to high-speed transceiver dies and HBM2; established EMIB production viability |
| Intel Agilex 7 / 9 / F-Series | FPGA family | Heterogeneous integration of FPGA logic, transceivers, HBM, and specialty dies via multiple EMIB bridges per package |
| Intel Sapphire Rapids (Xeon Max) | Server CPU with HBM | Bridges compute tiles to integrated HBM2e stacks; enables HBM-on-CPU server variant |
| Intel Ponte Vecchio (Max Series GPU) | AI/HPC GPU | Multiple EMIB bridges connect compute columns across the module; combined with Foveros for vertical tile stacking within each column |
| Subsequent Intel server and AI silicon | Roadmap products | EMIB continues as Intel's 2.5D workhorse for HBM-integrated server and AI silicon |
The FPGA segment is where EMIB has its deepest production heritage. FPGAs are natural candidates for heterogeneous integration — the fabric itself is most efficiently fabricated on a large-die leading-edge process, while transceivers, analog, and memory are best served by specialty process nodes. EMIB lets Intel/Altera fabricate each at its optimal node and integrate them in a single package with the necessary inter-die bandwidth. The Stratix 10 and Agilex families have iterated EMIB capability across multiple generations.
The Sapphire Rapids HBM variant is where EMIB demonstrated its server-CPU applicability. By embedding HBM stacks with EMIB bridges alongside the compute tiles, Intel delivered a server CPU with integrated high-bandwidth memory for HPC and AI workloads, without requiring a full silicon interposer. Ponte Vecchio's combined EMIB + Foveros integration at 40+ chiplets remains the most complex advanced packaging assembly Intel has shipped and continues to be cited as the flagship demonstration of multi-axis integration.
EMIB vs. CoWoS-L
EMIB and CoWoS-L share the structural concept — small silicon bridges embedded in an organic carrier rather than a full silicon interposer — and serve the same architectural niche: cost-optimized 2.5D integration. They differ in implementation, customer base, and maturity.
| Dimension | EMIB | CoWoS-L |
|---|---|---|
| Operator | Intel (captive for Intel products and IFS customers) | TSMC (captive for TSMC customers) |
| Production Heritage | Since Stratix 10 (2016); extensive product deployment across FPGA, server, and HPC | More recent addition to CoWoS family; ramping as cost-optimized variant alongside CoWoS-S |
| Primary Products | Intel FPGAs, server CPUs with HBM, Ponte Vecchio GPU, Intel advanced silicon | TSMC customer products requiring CoWoS-tier integration at reduced cost vs. CoWoS-S |
| Typical Pairing | Combined with Foveros for 2.5D + 3D modules | Part of the CoWoS family; customers may also use SoIC for 3D stacking |
Both architectures validate the bridge concept for cost-optimized 2.5D integration. The existence of two closely parallel bridge-based architectures at the two largest foundries suggests the approach has become structurally durable as a complement to full-interposer architectures like CoWoS-S.
Supply Chain & Equipment
| Input | Source | Notes |
|---|---|---|
| Silicon bridge fabrication | Intel captive back-end-of-line facilities | Bridges fabricated using damascene copper routing; wafer thinned and singulated into individual bridges |
| Substrate with embedded bridge | Ibiden, Unimicron, AT&S (qualified for EMIB bridge embedding) | Specialty process at substrate fabricator; Ibiden historical lead given long-standing Intel relationship |
| Die fabrication (compute tiles, HBM, transceivers) | Intel foundry for compute; external HBM suppliers; TSMC for select tiles in specific programs | Mix-and-match per product; Intel-fabricated compute often paired with externally-sourced HBM |
| Flip-chip attach equipment | BESI, ASMPT, Kulicke & Soffa; thermocompression bonders for fine-pitch bridge zones | Two-pitch alignment requires high-accuracy bonders at bridge zones |
| Module assembly and test | Intel captive advanced packaging facilities | Module test verifies multi-die functionality including bridge-routed interconnects |
Geographic Footprint
EMIB assembly runs at the same Intel advanced packaging facilities that host Foveros — Chandler, Arizona; Rio Rancho, New Mexico; Hillsboro, Oregon — plus additional capacity at Intel's Malaysia and Vietnam assembly sites for certain product lines. The U.S. concentration of EMIB production is a structural part of Intel's industrial-policy positioning; substrate supply flows in from Ibiden Japan, Unimicron Taiwan, and AT&S expansion in Malaysia and elsewhere.
EMIB is offered to external customers through Intel Foundry Services (IFS). Early IFS customer programs that use EMIB have been announced, alongside Foveros and the combined EMIB + Foveros offering. Customer adoption of EMIB outside Intel's own products is one of the strategic growth vectors for the technology; the captive production history and Intel-specific assembly discipline create qualification lead time for new external customers.
Market Outlook
EMIB demand growth tracks Intel's server CPU roadmap, AI silicon programs, FPGA product volume, and IFS external customer adoption. The technology is mature at the production level but continues to evolve — multiple bridges per package, tighter bridge pitch, and integration with next-generation substrate technology including glass substrates will extend EMIB's capability envelope. The combined EMIB + Foveros architecture remains a distinctive Intel offering and will continue as the default for multi-axis-integrated Intel products.
Competitively, EMIB shares the bridge-based 2.5D tier with CoWoS-L at TSMC and Samsung's parallel bridge architecture. The three approaches serve parallel customer bases through the remainder of this decade. The broader industry trend is that bridge-based 2.5D is growing alongside (not displacing) full-interposer 2.5D — the two serve different bandwidth tiers and will coexist as long as the AI accelerator tier needs full interposers while mid-performance multi-die products need the cost-optimized bridge option.
Related Coverage
Parent: Advanced Packaging
Companion Intel architecture: Foveros (3D stacking; pairs with EMIB in multi-axis modules)
Structural peer (TSMC): CoWoS-L (bridge-based variant within CoWoS family)
Peer 2.5D architectures: CoWoS-S / CoWoS-R (full interposer and RDL) · I-Cube
Foundation layers: Substrates & Interposers (silicon bridge detail) · Advanced Interconnects (micro-bump and fine-pitch bump interconnect)
Cross-architecture reference: Comparison Matrix