SemiconductorX > Chip Types > Compute & Logic > Quantum Compute
Quantum Semiconductors
Quantum computers exploit quantum mechanical phenomena — superposition, entanglement, and interference — to perform certain computations that are intractable for classical silicon. The semiconductor industry's role in quantum compute is not simply as a fabrication platform: quantum processors depend on semiconductor materials, lithographic patterning, thin-film deposition, and advanced packaging techniques borrowed from classical chip manufacturing, and the control electronics that operate qubits are themselves CMOS ICs that must function at cryogenic temperatures (4K or below). The supply chain for quantum compute is therefore a hybrid of classical semiconductor manufacturing and entirely new infrastructure: dilution refrigerators, cryogenic wiring, specialized superconducting materials, and an extremely limited global talent pool of quantum device engineers.
Quantum compute remains pre-commercial at scale. No quantum computer today can outperform a classical computer on a practically useful workload — the milestone of fault-tolerant, error-corrected quantum computation at commercially relevant qubit counts has not been reached. The supply chain story is therefore primarily about research infrastructure, fabrication dependencies, and the long-lead-time physical constraints (dilution refrigerator supply, isotopically pure silicon, superconducting film quality) that will gate commercial scaling when algorithmic and error-correction milestones are reached.
Quantum Computing Platforms — Technology & Status
| Platform / vendor | Flagship systems | Qubit technology & fabrication | Status & supply character |
|---|---|---|---|
| IBM Quantum | Eagle (127 qubits); Osprey (433 qubits); Condor (1,121 qubits, 2023); Heron r1/r2 (133 qubits, improved error rate, 2024); IBM Quantum System Two (modular, multi-QPU) | Superconducting transmon qubits; Josephson junctions on aluminum (Al) thin films patterned by electron-beam lithography; operates at ~15mK in dilution refrigerators; fabricated at IBM Research Yorktown Heights and Albany NanoTech | Cloud-accessible via IBM Quantum Network; largest deployed quantum compute fleet globally; Heron architecture separates QPU modules for modular scaling; IBM roadmap targets 100,000+ qubit systems via classical/quantum integration; most mature commercial quantum cloud offering |
| Google Quantum AI | Sycamore (53 qubits, 2019 "quantum supremacy" benchmark); Bristlecone (72 qubits); Willow (105 qubits, 2024 — exponential error suppression milestone); roadmap toward fault-tolerant million-qubit system | Superconducting transmon qubits; Al/Nb Josephson junctions; Google Santa Barbara research fab; operates at 15mK; Willow demonstrated below-threshold error scaling — first experimental evidence that adding qubits reduces error rate as quantum error correction theory predicts | Research program — limited cloud access; Willow's below-threshold error correction result (December 2024) is the most significant quantum hardware milestone since Sycamore's 2019 benchmark; practical fault-tolerant compute still years away; Google investing in dedicated quantum fab capacity |
| IonQ | IonQ Aria (25 algorithmic qubits, #AQ 25); IonQ Forte (35 #AQ, 2023); IonQ Forte Enterprise (2024); IonQ Tempo (next-gen, 2025 roadmap) | Trapped ytterbium ion qubits in room-temperature vacuum chambers with laser control; no dilution refrigerator required; CMOS photonics for laser delivery; IonQ's trapped ion approach is inherently all-to-all connected (no nearest-neighbor topology constraint of superconducting qubits) | Commercial — NASDAQ listed; cloud access via AWS Braket, Microsoft Azure Quantum, Google Cloud; highest gate fidelity per qubit of any commercial platform; qubit count scaling slower than superconducting; IonQ systems deployable in standard data center environments (no dilution refrigerator) |
| Quantinuum (Honeywell + Cambridge Quantum) | H1-1 / H1-2 (20 qubits, highest published two-qubit gate fidelity); H2 (56 qubits, 2023); H3 (next-gen, roadmap) | Trapped ytterbium ion qubits (similar to IonQ); QCCD (quantum charge-coupled device) architecture enables qubit shuttling for connectivity; Honeywell internal fab for ion trap fabrication | Commercial — cloud access via Azure Quantum, AWS; highest published two-qubit gate fidelity in industry; InQuanto chemistry simulation software; TKET quantum compiler; strong in quantum chemistry and optimization applications for pharmaceutical and materials research |
| PsiQuantum | Photonic qubit architecture targeting fault-tolerant million-qubit system; no announced qubit count milestones yet — company strategy is to build fault-tolerant at first rather than NISQ scaling | Silicon photonics — single-photon qubits generated by III-V quantum dot emitters (InAs in GaAs), routed through silicon photonic circuits, detected by superconducting nanowire single-photon detectors (SNSPDs); fabricated at GlobalFoundries (silicon photonics process) | Pre-commercial — raised $665M+ in funding; manufacturing partnership with GlobalFoundries for silicon photonic chip production; Australian government and US DOE partnerships; unique in being the only major quantum company using conventional semiconductor foundry (GF) for qubit chip production at commercial scale |
| Intel Silicon Spin Qubits | Intel Horse Ridge II (cryo-CMOS control IC, 4K operation); Tunnel Falls (12-qubit silicon spin qubit test chip, 2023); Intel Quantum SDK | Electron spins in isotopically purified Si-28 quantum dots; fabricated at Intel fabs using modified FinFET process; Horse Ridge cryo-CMOS control chip operates at 4K, reducing cryogenic wiring complexity; Intel's differentiation is fab integration — classical and quantum on same fab infrastructure | Research — no commercial quantum system; Intel's thesis is that CMOS-compatible spin qubits can scale using existing semiconductor fab infrastructure; qubit count and fidelity currently behind superconducting and trapped ion leaders; cryo-CMOS controller development is the most commercially relevant Intel quantum output currently |
| Microsoft Quantum | Topological qubit (Majorana-based, 2025 announcement); Azure Quantum (cloud platform, hosts IonQ and Quantinuum systems while Microsoft QPU develops) | Topological qubits using Majorana zero modes in hybrid semiconductor-superconductor nanowires (InAs/Al); Microsoft Station Q research; topological approach promises inherently error-protected qubits — if Majorana modes are stably induced, error correction overhead is dramatically reduced | Early experimental — Microsoft announced first topological qubit demonstration (February 2025) but no multi-qubit system or gate demonstrations; highest potential reward (error protection inherent to topology) but also highest technical risk; current Azure Quantum quantum compute is hosted IBM/IonQ/Quantinuum hardware |
Physical Supply Chain Dependencies
| Dependency | Required by | Supply chain status |
|---|---|---|
| Dilution refrigerators (~15mK) | All superconducting qubit systems (IBM, Google, Rigetti); silicon spin qubits at 15mK | Highly constrained — global supply dominated by Bluefors (Finland) and Oxford Instruments (UK); lead times 12–24 months; production capacity measured in hundreds of units per year; the physical infrastructure bottleneck for superconducting quantum compute scaling |
| Isotopically pure Si-28 | Silicon spin qubits (Intel, Delft, UNSW); reduces nuclear spin noise that decoherence spin qubits | Niche production — IsoSilicon (Russia, historically dominant), Urenco (centrifuge enrichment); small-volume specialty market; geopolitical supply chain concern given Russia sourcing history |
| Superconducting films (Al, Nb, NbTiN) | Josephson junction fabrication for superconducting qubits (IBM, Google); SNSPDs for photonic qubits (PsiQuantum) | Specialty deposition — requires ultra-low-defect thin films; fabricated in dedicated research fabs or modified semiconductor fabs; not a conventional semiconductor supply chain input |
| Cryo-CMOS control ICs | All qubit architectures at scale — classical control electronics must operate at 4K to reduce wiring harness from room temperature | Emerging — Intel Horse Ridge II is the most advanced commercial cryo-CMOS IC; standard CMOS process modified for 4K operation; supply chain follows conventional CMOS fab path once architectures mature |
| Silicon photonic foundry capacity (PsiQuantum) | PsiQuantum photonic qubit architecture; SNSPDs on silicon photonic platform | GlobalFoundries silicon photonics process (300mm); GF is the only major foundry with a production-ready silicon photonics process; PsiQuantum is GF's most high-profile quantum computing customer |
Commercial Horizon Assessment
The honest assessment of quantum compute commercialization is that the timeline to practical fault-tolerant quantum advantage on industrially relevant problems remains measured in years to decades, not months. The key milestones and their current status: error correction below threshold (Google Willow, December 2024 — achieved experimentally); logical qubit demonstration at scale (not yet demonstrated); fault-tolerant computation on useful problem (not yet demonstrated); quantum advantage on industrial optimization or simulation (not yet demonstrated).
The near-term commercial relevance of quantum compute for the SX focus sectors — AI training, inference, datacenter, AV, robotics, smart infrastructure — is minimal. The longer-term relevance is primarily in cryptography (Shor's algorithm threatens current RSA/ECC public key infrastructure, driving post-quantum cryptography standardization) and in materials simulation (drug discovery, battery electrolyte design, catalyst optimization) where quantum simulation has theoretical advantage over classical methods.
The supply chain infrastructure being built now — dilution refrigerator capacity, cryo-CMOS control IC development, isotopically pure silicon supply, and PsiQuantum's GF photonic foundry partnership — will determine which organizations can scale when algorithmic milestones are reached. That infrastructure investment is the strategically relevant supply chain signal, not near-term qubit shipment volumes.
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Cross-Network — ElectronsX Demand Side
Post-quantum cryptography standardization (NIST PQC standards finalized 2024) is creating a mandatory upgrade cycle for cryptographic hardware across EV OTA update systems, smart grid cybersecurity infrastructure, and V2X communication authentication — the quantum threat to current public key cryptography is a near-term driver of security silicon redesign even before quantum computers can break RSA at scale.
EX: EV Semiconductor Dependencies