Photolithography Step

Photolithography transfers a circuit pattern from a photomask onto the wafer. Light projected through the mask exposes a photoresist film on the wafer; chemical development then reveals the pattern, which subsequent etch or ion implantation steps transfer into the underlying material. Every patterned layer of every chip begins with a lithography step. A leading-edge logic chip with roughly 90 mask layers passes through 90 lithography cycles. DRAM and 3D NAND use fewer mask layers but still run lithography as the single most expensive and capacity-constrained operation in the fab.

Photolithography is the most concentrated supply chain in semiconductor manufacturing, full stop. ASML is the sole global supplier of EUV scanners. ASML produces approximately 50 to 60 standard EUV units per year — a rate that sets the physical upper bound on how fast the world can add leading-edge fab capacity. High-NA EUV at $380M per tool produces in even smaller volumes. The DUV market is slightly less concentrated (ASML leads with Canon and Nikon as competing suppliers for mid-range), but the advanced DUV immersion tools needed for 7nm-class multi-patterning come primarily from ASML. Below the scanner tier, Carl Zeiss SMT produces the optical systems — the single most sensitive sub-supplier in the EUV supply chain, with its own multi-year capacity expansion cycles. Trumpf and Cymer (ASML-owned) supply the high-power CO₂ lasers that drive the EUV plasma source.

The strategic weight of lithography is also its geopolitical weight. EUV scanner exports to China are subject to Dutch government license restriction in coordination with US policy, which in practice bans EUV to China. Advanced DUV immersion tools are similarly restricted. This bifurcates the global semiconductor manufacturing landscape: leading-edge nodes are accessible only to Western and allied-nation foundries; Chinese domestic production is structurally capped at DUV-achievable density (see Process Nodes & Lines).

The Lithography Workflow

A single lithography pass runs as a sequence on two tools: the coater-developer track (where the wafer is coated with photoresist, baked, developed, and cleaned) and the scanner (where the actual pattern exposure happens). The scanner and track are typically linked in a cluster configuration; the wafer moves between them automatically through the fab's wafer-handling system.

Once the wafer exits the track, it moves to the next process step (etch or ion implantation) to transfer the pattern into the underlying material. After that step, the remaining photoresist is stripped — covered as resist strip on the Wafer Cleaning page, since strip is chemistry-driven cleaning rather than lithography.

Lithography System Types

Three optical lithography generations plus two specialty approaches serve the current and near-future node landscape. Each has a specific wavelength, achievable resolution, and node applicability.

EUV in Depth

EUV lithography operates at a wavelength of 13.5 nm — in the soft X-ray regime, where no material is transparent and all optics must be reflective. This single physical fact drives the extraordinary engineering complexity of the EUV system, and explains why ASML is the sole supplier. An EUV scanner generates light by firing a high-power CO₂ laser at molten tin droplets 50,000 times per second, vaporizing each droplet into a plasma that emits 13.5 nm photons. Those photons are collected and focused by a chain of molybdenum-silicon multilayer mirrors — roughly a dozen mirrors per tool, each figured to near-atomic smoothness by Carl Zeiss SMT, because every surface imperfection degrades the image. The entire beam path is held in vacuum (EUV is absorbed by air). The wafer sits on a precision stage that moves beneath the projected image at roughly 700 mm/s.

A standard EUV scanner (ASML Twinscan NXE series) costs approximately $200 million and has a 12 to 18 month lead time from order to installation. ASML produces approximately 50 to 60 units per year. That production rate — not EUV's resolution or cost — is the binding constraint on how fast the world can add leading-edge fab capacity. Every new TSMC, Samsung, or Intel fab requires multiple EUV tools, and the allocation of ASML's annual output between customers is effectively the allocation of next-decade semiconductor capacity.

Canon and Nikon, both established lithography suppliers, spent years on EUV development before abandoning the effort. The engineering barriers — plasma source power, mirror precision, pellicle durability, overlay accuracy — took ASML more than twenty years and multi-billion-dollar partnerships with Intel, Samsung, and TSMC (as equity investors) to solve. A new EUV supplier from a standing start would face the same twenty-year development cycle; no second commercial EUV supplier is credible before the late 2030s at the earliest.

High-NA EUV

High-NA EUV is the next generation of EUV scanner, using a larger-aperture optical system (numerical aperture 0.55 versus 0.33 for standard EUV) to achieve finer resolution without changing wavelength. ASML's Twinscan EXE:5000 is the High-NA platform. Cost is approximately $380 million per tool. Intel was the first customer, with multiple High-NA systems installed at its Oregon development fab; TSMC and Samsung have also ordered High-NA EUV for sub-2 nm development. High-NA EUV is targeted at sub-2 nm production nodes (Intel 14A, TSMC A14, Samsung SF2 and beyond), with volume production expected from roughly 2027 onward.

High-NA EUV production rates are even more constrained than standard EUV — ASML targets roughly 20 units in 2025, ramping toward 30+ per year by 2027. Carl Zeiss SMT optics for High-NA (the anamorphic mirrors, which are physically larger and more complex than standard EUV optics) are the constraining sub-supplier. As with standard EUV, High-NA allocation between Intel, TSMC, and Samsung effectively determines who can develop and ramp the next generation of leading-edge nodes.

Multi-Patterning: The DUV Workaround

Below 28 nm, a single DUV exposure cannot print features at the required density. Multi-patterning is the response: the pattern for one logical layer is split across two, three, or four separate mask exposures, each printed at a relaxed pitch that DUV can handle, then merged during etch. Double patterning (LELE, LFLE), self-aligned double patterning (SADP), triple and quadruple patterning each add process steps, masks, and cost to every advanced layer. EUV's principal value proposition is that a single EUV exposure replaces multiple DUV exposures, reducing step count, mask count, and cycle time.

SMIC's N+1 (~7 nm class) process used for the Huawei Kirin 9010 demonstrates what extreme DUV multi-patterning can achieve without EUV access: roughly 7 nm equivalent density, at substantially lower throughput, higher cost, and lower yield than TSMC's EUV-based N7. This is the practical ceiling for Chinese domestic semiconductor manufacturing under current export controls. Further DUV multi-patterning research continues, but the density, yield, and economic penalties of extreme multi-patterning define a hard competitive floor that EUV-equipped foundries do not face.

The Photomask & Reticle Supply Chain

A lithography exposure requires a photomask — a quartz plate patterned with the circuit design for that specific layer. Each chip design requires a full mask set, typically 60 to 90+ masks at leading-edge nodes. Mask production is itself a specialized manufacturing operation with its own supply chain concentration.

EUV masks are structurally different from DUV masks — they are reflective rather than transmissive, built from alternating molybdenum and silicon multilayer stacks on a low-thermal-expansion substrate. A single EUV mask costs several hundred thousand dollars; a full EUV mask set for a leading-edge chip design runs into millions. Mask costs compound across mask revisions during bring-up, making EUV mask economics a significant portion of the overall non-recurring engineering cost for a new chip design. See Photomasks and Photomask Deliverables for the Materials & IP side.

Equipment & Ecosystem

The lithography ecosystem includes the scanner itself, the coater-developer track, the optical and source systems inside the scanner, the mask and resist infrastructure, and alignment and metrology. Concentration at each layer compounds the overall supply chain tightness.

Materials

Photolithography consumes three classes of materials. Photoresist is the light-sensitive film coated on the wafer — chemistry is matched to the lithography wavelength, and EUV resist is a distinct specialty supply with only three qualified volume suppliers. The Photoresist child page covers this in depth. Developer (typically tetramethylammonium hydroxide, TMAH, at specific concentrations) dissolves exposed or unexposed resist to reveal the pattern. Anti-reflective coatings (BARC for bottom, TARC for top) prevent standing-wave and reflectivity effects during exposure that would otherwise distort the pattern. See Process Consumables and Critical Chemicals for the supply chain view of these materials.

Alternative Lithography Approaches

Several alternatives to optical lithography exist in research and niche production. None is positioned to displace EUV for leading-edge high-volume manufacturing within the current planning horizon, but each has potential in specific applications.

Export Controls & Geopolitical Framing

Photolithography is the primary instrument of semiconductor export control policy. The Dutch government, in coordination with US policy, restricts exports of EUV scanners to China; no ASML EUV tool has been delivered to a Chinese customer. Advanced DUV immersion scanners (ASML NXT:2000i and above) also require export licenses that have increasingly been denied. These restrictions, together with US restrictions on advanced deposition and etch equipment, create a hard ceiling on Chinese domestic semiconductor manufacturing capability at roughly the 7 nm DUV-multi-patterning level.

The structural consequence is bifurcated global semiconductor manufacturing: leading-edge capability at TSMC, Samsung, and Intel; mature-to-advanced capability at Chinese domestic foundries with no realistic near-term path to close the gap. This bifurcation widens with every new EUV and High-NA EUV generation, as leading-edge density advances in ways that DUV-only processes cannot match through any amount of multi-patterning. See Process Nodes & Lines and U.S. Reshoring for deeper coverage.

Related Coverage

Parent: Front-End Fabrication

Peers in front-end: Wafer Cleaning · Oxidation · Deposition · Etching · Doping · CMP · Metrology

Lithography materials: Photoresist

Photomask supply chain (Materials & IP): Photomasks · Photomask Deliverables

Equipment: WFE Hub · Process Consumables

Cross-pillar dependencies: Process Nodes & Lines · U.S. Reshoring · Bottleneck Atlas