Fab & Assembly — Semiconductor Manufacturing Overview

Fab & Assembly is where inputs become chips and chips become modules. A polished wafer enters at one end of this pillar; a tested, system-ready semiconductor module exits at the other. Between those two points lies the most capital-intensive, geographically concentrated manufacturing sequence in the industrial world — in roughly 1,000 fabs globally, of which only a few dozen operate at leading-edge nodes".

Fab & Assembly begins where Materials & IP ends — polished wafer at the load port, mask set at the lithography bay, qualified consumables at the fab dock. It ends where Chip Types begins — tested, packaged, system-ready device. Supporting infrastructure (power, ultrapure water, cleanroom HVAC, gas delivery, vacuum, emissions abatement) is covered in Fab OPS. Consumables appear here and in Materials & IP through different lenses: supply chain upstream, in-process integration here.

Manufacturing Flow — Wafer In to Module Out

Four sequential stages, one continuous production flow. The product is not done until it is packaged and integrated.

Stage	What Happens	Primary Supply Chain Character
Front-End Fabrication	500–1,000 process steps transform the blank wafer into a wafer of working transistors and interconnects; lithography, deposition, etch, CMP, implant, metrology	Highest CapEx ($15–25B per leading-edge fab); TSMC Taiwan geographic concentration; EUV sole-source; KLA metrology near-sole-source
Wafer Test (Sort)	Electrical test of every die on the wafer before dicing; yield identification; first economic gate	Advantest-Teradyne ATE duopoly; probe card supply tightening (FormFactor, MJC, Technoprobe); test data feeds process control loop
Back-End Assembly & Advanced Packaging	Dicing, die attach, wire bond and flip-chip interconnect, encapsulation; CoWoS, SoIC, Foveros, EMIB, InFO, FOPLP; die stacking with HBM; substrate integration	TSMC CoWoS is the AI accelerator binding constraint; ABF laminate near-sole-source (Ajinomoto); hybrid bonding equipment concentrated with Besi; OSAT landscape led by ASE, Amkor, JCET
Module Integration	Packaged die combined with passives, connectors, heat spreaders, and PCB into compute modules, memory modules, power modules, sensor modules; module-level test	Traditionally separated from front-end by geography; Terafab vertical integration thesis collapses the boundary for strategic programs (AI6, AI7)

Geographic Concentration — Where Chips Are Made

Region	Primary Fab Capability	Strategic Risk Profile
Taiwan	Leading-edge logic (TSMC N3/N2/N5 — ~90% of sub-5nm globally); advanced packaging (TSMC CoWoS, InFO); mature node (UMC, PSMC, Vanguard)	Taiwan Strait geopolitical risk is the primary systemic semiconductor supply chain risk globally; no Western alternative at N3/N5 through 2030
South Korea	Leading-edge logic (Samsung N3/N4); DRAM (Samsung, SK hynix); HBM (SK hynix dominant); NAND (Samsung, SK hynix)	HBM concentration at SK hynix for AI GPU programs; Samsung logic yield gap vs. TSMC at N3; China revenue exposure
Japan	Specialty analog and power (Renesas, Rohm); image sensors (Sony Kumamoto); NAND (Kioxia Yokkaichi); TSMC Japan N28/N6 (Kumamoto); Rapidus 2nm (Chitose)	Renesas Naka fire precedent; Sony Kumamoto earthquake zone; Rapidus 2nm timeline highly uncertain
United States	Mature analog and power (TI Sherman, NXP Austin); leading-edge ramping (TSMC Arizona, Intel Ohio, Samsung Taylor); SiC (Wolfspeed, onsemi); GlobalFoundries Malta	Leading-edge capacity ramping but years from TSMC Taiwan scale; CHIPS Act funding flowing; workforce and ecosystem are the long lead items
Europe	Automotive MCU (Infineon Dresden, STMicro Crolles/Tours, NXP Hamburg); SiC (Infineon Villach, STMicro Catania, Bosch Dresden); ASML (equipment, not fab)	Automotive-grade mature node — right product, wrong scale for leading-edge; EU Chips Act targeting buildout; TSMC Dresden is the most credible near-term path
China	Mature logic (SMIC, Hua Hong); memory (CXMT DRAM, YMTC NAND); power and analog domestic expansion; limited leading-edge via DUV multi-patterning	EUV blocked — SMIC leading-edge limited by DUV ceiling; strongest position at mature node where automotive and analog demand lives; mature capacity is the asymmetric lever

Fab & Assembly Layers

Fab Facilities
Facilities where transformation happens. Fab archetypes across leading-edge logic, mature logic, DRAM, 3D NAND, SiC and GaN power, analog, CMOS image sensor, MEMS, III-V compound, and silicon photonics. OSAT and captive packaging operators. Test facilities as an emerging standalone layer.

Fab Equipment
Tools that execute the transformation. WFE for front-end processing — lithography, etch, deposition, CMP, metrology. Packaging equipment — hybrid bonding, die attach, fan-out, substrate production. Test equipment — ATE, probe cards, handlers.

Fab Process Consumables
The in-process integration lens. Process gases, photoresist, CMP slurries, sputtering targets, silicon wafers — as consumed at the point of use, not as sourced from upstream suppliers. Supply-chain view lives in Materials & IP.

Manufacturing Process Flow
The sequence that moves the wafer through the fab. Four segments — Front-End Fabrication, Wafer Test (Sort), Back-End Assembly & Packaging, Module Integration — one continuous production flow from polished wafer to tested module. The front-end segment runs as a layer-build loop repeated 80 to 120 times per wafer; the downstream segments run once per die or once per module.

The Fabs

The fab database is the primary reference asset for this layer — individual profile pages for every major semiconductor fab globally, organized by operator, location, wafer size, process node, technology type, and strategic status. Each profile covers capacity, capital investment, CHIPS Act subsidy status, key customers and programs, energy and water consumption, geopolitical risk rating, and operational timeline.

Fab List — directory of global semiconductor fabs
Fab Clusters — geographic cluster analysis (Taiwan, South Korea, Japan, US, Europe, China)
Fab Spotlight

Cross-Network — ElectronsX Demand Side

The Fab & Assembly layer produces the chips that every EX supply chain depends on. TSMC Arizona producing AI5 for Tesla vehicles and datacenter inference connects to EX's SDV and autonomy coverage. Wolfspeed's Mohawk Valley fab producing SiC power modules connects to EX's power electronics and BESS supply chain pages. Samsung Taylor operating as Tesla's captive fab for AI5 connects to the Terafab story across both networks.

EX: Power Electronics & HV/LV Stack | EX: SDV Systems Supply Chain | EX: Tesla Terafab & Silicon Strategy | EX: Electrification Bottleneck Atlas

Related Coverage

Upstream layer: Materials & IP — inputs that flow into the fab

Downstream layers: Chip Types — what the fab produces | Sectors — where finished chips are deployed

SX Editorial: Semiconductor Bottleneck Atlas | Tesla Terafab — Supply Chain |

SX Fab OPS: FAB OPS — power, water, HVAC, emissions, seismic