Process Nodes

Process nodes are the most cited specification in semiconductor manufacturing and the most misunderstood. When TSMC announces N3, Samsung announces SF3, and Intel announces 18A, they are describing three different transistor architectures, lithography configurations, and density achievements that happen to share a number. The "nm" number has not corresponded to any physical transistor dimension since approximately 2009. What process node names describe today is a combination of transistor density (typically measured in millions of transistors per square millimeter), power efficiency, and performance capability relative to the previous generation — not a gate length, fin pitch, or any specific geometric feature. TSMC N3E achieves roughly 167 MTr/mm² with a ~9 nm physical gate length. Samsung SF3 uses a more advanced transistor architecture (GAA) than TSMC N3 but at lower density. Intel 18A uses GAA plus backside power delivery and targets competitiveness with TSMC N2 despite a different name.

The SX lens on process nodes is supply chain concentration, not transistor physics. Three structural facts dominate. First, TSMC manufactures approximately 90% of all chips at sub-5 nm nodes globally — the single most concentrated chokepoint in the semiconductor supply chain. Second, ASML is the sole global supplier of EUV lithography scanners without which no leading-edge process node can be manufactured at volume, and the ~50–60 EUV scanners per year ASML produces is the physical upper bound on how fast the world can add EUV-enabled fab capacity. Third, the capital cost of a new leading-edge fab runs $15–20 billion with a 3–5 year construction timeline, meaning no supply shortage at advanced nodes can be resolved on a timescale shorter than a new fab's lead time. Foundry concentration, lithography monopoly, and capital lead time define the risk profile of the leading-edge tier more than any transistor specification.

The Lithography Ladder

Lithography — projecting circuit patterns onto silicon using light — is the primary gating variable for process node advancement. Three lithography generations define the current and near-future landscape.

ASML's EUV monopoly is not a market failure but a reflection of extraordinary engineering difficulty: generating sufficient EUV power requires firing a CO₂ laser at tin droplets 50,000 times per second to create a plasma that emits 13.5 nm photons, focused through reflective Mo–Si multilayer mirrors in a vacuum system the size of a bus. Canon and Nikon both spent years on EUV development before abandoning the effort. A second commercial EUV supplier within this decade is implausible.

Transistor Architecture Progression

Process node advancement over the modern era has been driven more by transistor architecture innovation than by dimensional scaling. Three architectural generations define the current landscape: planar MOSFET (dominant through 22 nm, 2011–2012); FinFET (Intel at 22 nm in 2012; TSMC and Samsung at 16/14 nm in 2014–2015; still the dominant architecture at TSMC N3 production today); and gate-all-around (GAA) nanosheet (Samsung SF3 in 2022 as first commercial GAA, TSMC N2 in 2025, Intel 18A in 2026). Each generation improves electrostatic gate control over the transistor channel as dimensional scaling alone became insufficient. Backside power delivery — moving power rails from the front side (where they compete with signal routing) to the back of the wafer — debuts at Intel 18A (called PowerVia) and is expected on future TSMC and Samsung nodes. Detailed architecture treatment is deferred to a dedicated Transistor Architectures page.

The Node Naming Problem

The absence of any industry standard for process node naming is a persistent source of confusion. Each foundry uses its own convention, and the same number describes meaningfully different manufacturing capabilities. TSMC N-prefix names (N7, N5, N3, N2) track internal process generations. Samsung SF-prefix names (SF5, SF4, SF3, SF2) may represent more advanced transistor architecture (SF3 was the first GAA node) but at lower density than TSMC N3E. Intel's naming has reset multiple times; current conventions use numeric identifiers (Intel 4, Intel 3, Intel 18A) that align by performance-equivalence rather than geometry. The correct comparison across foundries requires transistor density (MTr/mm²), transistor architecture (FinFET vs. GAA), lithography used, and yield maturity — not the node number alone.

Foundry Reference Table — Leading-Edge Tier

The table below summarizes currently-shipping and near-term leading-edge nodes at the three foundries producing below 5 nm. Mature-node specialty foundries (GlobalFoundries, UMC, Tower, SMIC's mature portfolio, Hua Hong) compete at 14 nm and above and are covered at Mature & Legacy Nodes.

Mature and Legacy Nodes

The leading-edge node race captures industry narrative but mature and legacy nodes (28 nm and above) manufacture the majority of semiconductor units shipped globally and serve markets with no alternative at any price. Automotive MCUs, industrial sensor ICs, power management analog, RF front-end modules, display drivers, and mil-spec rad-hard devices all require nodes from 28 nm to 180 nm and above. The 2021–2023 semiconductor shortage was primarily a mature-node crisis — vehicle production halted due to shortages of $1 MCUs at 90–130 nm, not AI GPUs at N4. The 28 nm node is the most strategically contested mature node: it is the boundary below which EUV is beneficial and above which DUV is adequate, it is manufacturable at every major foundry including SMIC, and it is the de facto frontier of China's semiconductor self-sufficiency program. See Mature & Legacy Nodes for full coverage.

Export Controls

Process node technology has become a primary instrument of US-China geopolitical competition. The US export control regime restricts China's access to EUV scanners (full ban — Netherlands government enforcement aligned with US policy), advanced DUV scanners (license required for ASML's highest-performance systems), advanced fab equipment from Applied Materials, Lam Research, and KLA, advanced AI chips (NVIDIA H100/B-series and equivalent), and EDA software for advanced node design. The practical consequence is a bifurcated global semiconductor capability: Western and allied foundries (TSMC, Samsung, Intel) access the full EUV and High-NA EUV stack; Chinese domestic foundries (SMIC, Hua Hong, CXMT) are capped at approximately 7 nm-equivalent density achievable via DUV multipatterning. The gap widens with each new EUV generation.

Specialty Process Lines

A substantial fraction of the semiconductor supply chain operates on specialty process lines optimized for performance dimensions other than transistor density. SiC and GaN process lines manufacture wide-bandgap power semiconductors physically impossible on standard silicon CMOS — Wolfspeed, STMicro, Infineon, Onsemi operate dedicated SiC fabs at equivalent feature sizes of 500 nm–1 µm. SiGe BiCMOS lines (GlobalFoundries Malta NY, IHP Frankfurt-Oder) enable transistors with transition frequencies above 300 GHz required for 77 GHz automotive radar and 5G mmWave. GaAs, InP, GaN-on-SiC compound semiconductor process lines at WIN Semiconductors, Qorvo, Skyworks, and defense specialty fabs serve RF applications from cellular handset PAs through defense radar T/R modules. These specialty lines are not comparable to logic nodes by any density metric but are critical to the overall semiconductor supply chain.

Related Coverage

Parent: Fab & Assembly

Related fab topics: Wafer Fab Equipment (WFE) · Photolithography · Mature & Legacy Nodes

Specialty process lines: SiC & GaN · RF Semiconductors