PDK & Process Design Kits

A Process Design Kit (PDK) is the technical bridge between a foundry's manufacturing process and a chip designer's EDA tools. It encodes everything a designer needs to correctly model, simulate, place, route, and verify a chip for a specific foundry node: transistor SPICE models, standard cell libraries, design rule manuals, physical verification runsets, layout parasitics, and IP validation data. Without a PDK, a chip designer cannot produce mask-ready layout that will actually yield correctly in silicon. PDKs are provided by foundries to qualified customers -- making PDK access a gatekeeping mechanism and foundry lock-in instrument as powerful as any contractual commitment.

What a PDK Contains

PDK as Foundry Competitive Moat

TSMC's PDK infrastructure -- delivered through its Open Innovation Platform (OIP) -- is one of the most powerful competitive moats in the semiconductor industry. TSMC's PDKs are the most extensively validated, most broadly tested, and most deeply integrated with the EDA tools and IP ecosystem of any foundry. When a chip designer starts a new design project, they choose a foundry PDK first -- all subsequent design decisions (which EDA tools, which IP blocks, which standard cell library) flow from that foundry choice. A chip designed for TSMC's N3 PDK cannot be ported to Samsung's 3GAE or Intel's 18A process without a near-complete redesign: different design rules, different device models, different standard cell architecture, different verified IP.

This porting cost -- estimated as a multi-year, multi-million-dollar undertaking for complex SoCs -- is the primary mechanism by which TSMC retains customers across product generations. A company that designed its flagship product on TSMC N5 and invested in N5-validated IP will almost certainly design the next generation on TSMC N3 or N2 rather than port to a competitor's process, because the PDK migration cost would be enormous and the yield learning curve at a new foundry would set back time-to-market by years.

TSMC Open Innovation Platform (OIP)

TSMC's OIP ecosystem formalizes the PDK-as-moat strategy by creating a curated, TSMC-certified network of EDA tools, IP vendors, and design service companies that are validated to work with TSMC PDKs. OIP covers: certified EDA tool flows from Synopsys, Cadence, and Siemens; silicon-validated IP from hundreds of IP vendors covering CPU, memory, PHY, analog, and security blocks; and design methodology support including reference flows, design-for-manufacturing (DFM) guidelines, and OPC models. The 3DFabric Alliance extension of OIP covers 3D chip stacking, CoWoS, and chiplet interfaces -- extending the ecosystem lock-in into advanced packaging.

OIP's effect is to make TSMC not just a wafer producer but an integrated design infrastructure platform. A chip designed using OIP resources benefits from TSMC-guaranteed interoperability between PDK, EDA tools, and IP -- reducing design risk and tape-out cycle time. This risk reduction is a direct competitive advantage that Samsung and Intel Foundry have struggled to match, because they have smaller IP ecosystems, fewer certified EDA tool partnerships, and less accumulated process knowledge embedded in their PDKs.

Samsung & Intel Foundry PDK Landscape

Samsung Foundry provides PDKs for its process nodes (SF3, SF2, SF2P for GAA-based nodes) and has its own ecosystem program (Samsung Advanced Foundry Ecosystem, SAFE). Samsung's PDK ecosystem is substantially smaller than TSMC's -- fewer certified IP vendors, fewer EDA tool validations, and less silicon-proven IP at leading nodes. Samsung's first-time tape-out success rate challenges have been widely discussed in the industry, reflecting in part the lower PDK ecosystem maturity compared to TSMC. Intel Foundry (IFS) is the newest entrant to the merchant foundry PDK ecosystem, offering PDKs for Intel 18A and Intel 16 processes. Intel's PDK ecosystem is the least developed of the three -- it has a smaller IP vendor base, limited OIP-equivalent certification infrastructure, and has not yet demonstrated the foundry-side yield maturity that instills designer confidence.

Open PDK Initiatives

The open PDK movement -- led by initiatives like Google's collaboration with SkyWater Technology (sky130 open PDK) and GlobalFoundries/Efabless programs -- makes process design kits publicly available for mature nodes (130nm, 65nm). These open PDKs enable academic research, startup prototyping, and open-source hardware development without the NDA and access barriers of leading-edge foundry PDKs. Open PDKs have no commercial relevance at advanced nodes (3nm, 2nm) where the process complexity and IP investment are too large to make public release viable, but they have been meaningful for democratizing chip design education and enabling low-cost silicon prototyping for emerging applications.

PDK Access Control & Customer Qualification

Leading-edge foundry PDKs are not publicly available. Access requires signing a non-disclosure agreement (NDA) with the foundry, demonstrating design intent (the foundry must be convinced the customer has a viable product plan that will generate wafer revenue), and in some cases completing a formal customer qualification process. This access control is intentional -- it protects the foundry's process IP (the design rules and device models encode the foundry's manufacturing knowledge) and ensures that PDK data does not leak to competitors or governments with hostile intent. US export control law treats certain foundry PDK data as controlled technology, particularly for leading-edge nodes where the process knowledge embedded in the PDK could advance a foreign adversary's semiconductor manufacturing capability.

Supply Chain Outlook

PDK lock-in is the semiconductor industry's most durable customer retention mechanism. Unlike equipment or chemical supply agreements, which can be renegotiated or re-sourced, PDK migration requires redesigning the chip from physical layout upward -- a commitment that spans years and tens to hundreds of millions of dollars. This lock-in dynamic benefits TSMC most, because its PDK ecosystem's head start in certified IP and EDA tool coverage widens rather than narrows with each new node. The 3DFabric extension of OIP into advanced packaging means that as chiplet architectures become standard, the OIP ecosystem expands its scope to encompass multi-die system integration -- further deepening the customer dependency on TSMC's design infrastructure.

Related Coverage

Fabless Design & IP Overview | IP Licensing | EDA Tools | Materials & IP Hub | Bottleneck Atlas